P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet - Page 50

• Manufacturer Part Number: P60ARM-B
• Description: 32-bit RISC microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

P60ARM-B
STM instructions take (n-1)S + 2N incremental cycles to execute.
n
4.8.9 Assembler syntax
<LDM|STM>{cond}<FD|ED|FA|EA|IA|IB|DA|DB> Rn{!},<Rlist>{^}
{cond} - two character condition mnemonic, see Figure 6: Condition Codes
Rn is an expression evaluating to a valid register number
<Rlist> is a list of registers and register ranges enclosed in {} (eg {R0,R2-R7,R10}).
{!} if present requests write-back (W=1), otherwise W=0
{^} if present set S bit to load the CPSR along with the PC, or force transfer of user bank when in privileged
mode
Addressing mode names
There are different assembler mnemonics for each of the addressing modes, depending on whether the
instruction is being used to support stacks or for other purposes. The equivalences between the names and
the values of the bits in the instruction are shown in the following table:
FD, ED, FA, EA define pre/post indexing and the up/down bit by reference to the form of stack required.
The F and E refer to a ÒfullÓ or ÒemptyÓ stack, i.e. whether a pre-index has to be done (full) before storing
to the stack. The A and D refer to whether the stack is ascending or descending. If ascending, a STM will go
up and LDM down, if descending, vice-versa.
46
is the number of words transferred.
pre-increment load
post-increment load
pre-decrement load
post-decrement load
pre-increment store
post-increment store
pre-decrement store
post-decrement store
name
Table 5: Addressing Mode Names
LDMED
LDMFD
LDMEA
LDMFA
STMFA
STMEA
STMFD
STMED
stack
LDMIB
LDMIA
LDMDB
LDMDA
STMIB
STMIA
STMDB
STMDA
other
L bit
1
1
1
1
0
0
0
0
P bit
1
0
1
0
1
0
1
0
U bit
1
1
0
0
1
1
0
0