P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet - Page 83

• Manufacturer Part Number: P60ARM-B
• Description: 32-bit RISC microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

7.5 Store register
The first cycle of a store register is similar to the first cycle of load register. During the second cycle the base
modification is performed, and at the same time the data is written to memory. There is no third cycle. The
cycle timings are shown below in Table 11: Store Register Instruction Cycle Operations. The base write-back
is prevented during a Data Abort if the processor is configured for Early Abort. The write-back is not
prevented if Late Abort is configured.
7.6 Load multiple registers
The first cycle of LDM is used to calculate the address of the first word to be transferred, whilst performing
a prefetch from memory. The second cycle fetches the first word, and performs the base modification.
During the third cycle, the first word is moved to the appropriate destination register while the second
word is fetched from memory, and the modified base is latched internally in case it is needed to patch up
after an abort. The third cycle is repeated for subsequent fetches until the last data word has been accessed,
then the final (internal) cycle moves the last word to its destination register. The cycle timings are shown in
Table 12: Load Multiple Registers Instruction Cycle Operations.
The last cycle may be merged with the next instruction prefetch to form a single memory N-cycle.
If an abort occurs, the instruction continues to completion, but all register writing after the abort is
prevented. The final cycle is altered to restore the modified base register (which may have been overwritten
by the load activity before the abort occurred).
When the PC is in the list of registers to be loaded the current instruction pipeline must be invalidated.
Note that the PC is always the last register to be loaded, so an abort at any point will prevent the PC from
being overwritten.
Cycle
1
2
pc+8
alu
pc+12
Address
Table 11: Store Register Instruction Cycle Operations
nBW
b/w
1
nRW
0
1
Instruction Cycle Operations
(pc+8)
Data
Rd
nMREQ
0
0
SEQ
0
0
nOPC
0
1
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