P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet - Page 79

• Manufacturer Part Number: P60ARM-B
• Description: 32-bit RISC microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

7.0 Instruction Cycle Operations
In the following tables nMREQ and SEQ (which are pipelined up to one cycle ahead of the cycle to which
they apply) are shown in the cycle in which they appear, so they predict the type of the next cycle. The
address, nBW, nRW, and nOPC (which appear up to half a cycle ahead) are shown in the cycle to which
they apply.
Key:-
7.1 Branch and branch with link
A branch instruction calculates the branch destination in the first cycle, whilst performing a prefetch from
the current PC. This prefetch is done in all cases, since by the time the decision to take the branch has been
reached it is already too late to prevent the prefetch.
During the second cycle a fetch is performed from the branch destination, and the return address is stored
in register 14 if the link bit is set.
The third cycle performs a fetch from the destination + 4, refilling the instruction pipeline, and if the branch
is with link R14 is modified (4 is subtracted from it) to simplify return from SUB PC,R14,#4 to MOV PC,R14.
This makes the STM..{R14} LDM..{PC} type of subroutine work correctly. The cycle timings are shown
below in Table 7: Branch Instruction Cycle Operations
7.2 Data Operations
A data operation executes in a single datapath cycle except where the shift is determined by the contents of
a register. A register is read onto the A bus, and a second register or the immediate field onto the B bus. The
ALU combines the A bus source and the shifted B bus source according to the operation specified in the
instruction, and the result (when required) is written to the destination register. (Compares and tests do not
produce results, only the ALU status flags are affected.)
(pc)
Xn
Cycle
1
2
3
=
=
pc is the address of the branch instruction
alu is an address calculated by ARM60
(alu) are the contents of that address, etc
contents of the pc.
exception vector
Address
alu+4
alu+8
pc+8
alu
Table 7: Branch Instruction Cycle Operations
nBW
1
1
1
nRW
0
0
0
¥
Instruction Cycle Operations
=
(alu + 4)
(pc + 8)
a varying number
Data
(alu)
nMREQ
0
0
0
SEQ
0
1
1
nOPC
0
0
0
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