P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet - Page 3

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P60ARM-B

Manufacturer Part Number
P60ARM-B
Description
32-bit RISC microprocessor
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet
1.0
2.0
3.0
4.0
5.0
6.0
7.0
Introduction
1.1
1.2
Signal Description
Programmer's Model
3.1
3.2
3.3
3.4
3.5
Instruction Set
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
Memory Interface
5.1
5.2
5.3
5.4
5.5
5.6
Coprocessor Interface
6.1
6.2
6.3
6.4
6.5
6.6
Instruction Cycle Operations
7.1
7.2
7.3
7.4
7.5
ARM60 Block diagram
ARM60 Functional Diagram
Hardware Configuration
Operating Mode Selection
Registers
Exceptions
Reset
Instruction Set Summary
The Condition Field
Branch and Branch with link (B, BL)
Data processing
PSR Transfer (MRS, MSR)
Multiply and Multiply-Accumulate (MUL, MLA)
Single data transfer (LDR, STR)
Block data transfer (LDM, STM)
Single data swap (SWP)
Software interrupt (SWI)
Coprocessor data operations (CDP)
Coprocessor data transfers (LDC, STC)
Coprocessor register transfers (MRC, MCR)
Undefined instruction
Instruction Set Examples
Cycle types
Byte addressing
Address timing
Memory management
Locked operations
Stretching access times
Interface signals
Data transfer cycles
Register transfer cycle
Privileged instructions
Idempotency
Undefined instructions
Branch and branch with link
Data Operations
Multiply and multiply accumulate
Load register
Store register
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