P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet - Page 87

• Manufacturer Part Number: P60ARM-B
• Description: 32-bit RISC microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

7.10 Coprocessor data operation
A coprocessor data operation is a request from ARM60 for the coprocessor to initiate some action. The
action need not be completed for some time, but the coprocessor must commit to doing it before driving
CPB LOW.
If the coprocessor can never do the requested task, it should leave CPA and CPB HIGH. If it can do the task,
but can't commit right now, it should drive CPA LOW but leave CPB HIGH until it can commit. ARM60
will busy-wait until CPB goes LOW. The cycle timings are shown in Table 16: Coprocessor Data Operation
Instruction Cycle Operations.
7.11 Coprocessor data transfer (from memory to coprocessor)
Here the coprocessor should commit to the transfer only when it is ready to accept the data. When CPB goes
LOW, ARM60 will produce addresses and expect the coprocessor to take the data at sequential cycle rates.
The coprocessor is responsible for determining the number of words to be transferred, and indicates the last
transfer cycle by driving CPA and CPB HIGH.
ARM60 spends the first cycle (and any busy-wait cycles) generating the transfer address, and performs the
write-back of the address base during the transfer cycles. The cycle timings are shown in Table 17:
Coprocessor Data Transfer Instruction Cycle Operations.
not ready
ready
Cycle
1
1
2
n
•
Table 16:
Address
pc+8
pc+12
pc+8
pc+8
pc+8
pc+8
pc+12
Coprocessor Data Operation Instruction Cycle Operations
nBW
1
1
1
1
1
nRW
0
0
0
0
0
(pc+8)
(pc+8)
Data
Instruction Cycle Operations
-
-
-
nMREQ
0
1
1
1
0
SEQ
0
0
0
0
0
nOPC
0
0
1
1
1
nCPI
0
0
0
0
0
CPA
0
0
0
0
0
CPB
83
0
1
1
1
0