P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet - Page 86

• Manufacturer Part Number: P60ARM-B
• Description: 32-bit RISC microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

P60ARM-B
7.9 Software interrupt and exception entry
Exceptions (and software interrupts) force the PC to a particular value and refill the instruction pipeline
from there. During the first cycle the forced address is constructed, and a mode change may take place. The
return address is moved to R14 and the CPSR to SPSR_svc.
During the second cycle the return address is modified to facilitate return, though this modification is less
useful than in the case of branch with link.
The third cycle is required only to complete the refilling of the instruction pipeline. The cycle timings are
shown below in Table 15: Software Interrupt Instruction Cycle Operations.
For software interrupts, pc is the address of the SWI instruction. For interrupts and reset, pc is the address
of the instruction following the last one to be executed before entering the exception. For prefetch abort, pc
is the address of the aborting instruction. For data abort, pc is the address of the instruction following the
one which attempted the aborted data transfer. Xn is the appropriate trap address.
82
Cycle
Cycle
1
2
3
1
2
3
4
Address
pc+8
Xn
Xn+4
Xn+8
Address
pc+8
Rn
Rn
pc+12
pc+12
Table 15: Software Interrupt Instruction Cycle Operations
Table 14: Data Swap Instruction Cycle Operations
nBW
nBW
1
1
1
b/w
b/w
1
1
nRW
nRW
0
0
0
0
0
1
0
(Xn+4)
(pc+8)
Data
(Xn)
(pc+8)
Data
(Rn)
Rm
-
nMREQ
nMREQ
0
0
0
0
0
1
0
SEQ
SEQ
0
1
1
0
0
0
1
nOPC
nOPC
0
0
0
0
1
1
1
nTRANS
LOCK
1
1
1
0
1
1
0