P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet - Page 20

• Manufacturer Part Number: P60ARM-B
• Description: 32-bit RISC microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

P60ARM-B
3.4.6 Vector Summary
These are byte addresses, and will normally contain a branch instruction pointing to the relevant routine.
The FIQ routine might reside at 0x1C onwards, and thereby avoid the need for (and execution time of) a
branch instruction.
The reserved entry is for an Address Exception vector which is only operative when the processor is
configured for a 26 bit program space. See 13.0 Appendix - Backward Compatibility
3.4.7 Exception Priorities
When multiple exceptions arise at the same time, a fixed priority system determines the order in which they
will be handled:
(1)
(2)
(3)
(4)
(5)
(6)
Note that not all exceptions can occur at once. Undefined instruction and software interrupt are mutually
exclusive since they each correspond to particular (non-overlapping) decodings of the current instruction.
If a data abort occurs at the same time as a FIQ, and FIQs are enabled (i.e. the F flag in the CPSR is clear),
ARM60 will enter the data abort handler and then immediately proceed to the FIQ vector. A normal return
from FIQ will cause the data abort handler to resume execution. Placing data abort at a higher priority than
FIQ is necessary to ensure that the transfer error does not escape detection; the time for this exception entry
should be added to worst case FIQ latency calculations.
16
Reset (highest priority)
Data abort
FIQ
IRQ
Prefetch abort
Undefined Instruction, Software interrupt (lowest priority)
0x00000000
0x00000004
0x00000008
0x0000000C
0x00000010
0x00000014
0x00000018
0x0000001C
Address
Reset
UndeÞned instruction
Software interrupt
Abort (prefetch)
Abort (data)
-- reserved --
IRQ
FIQ
Table 3: Vector Summary
Exception
Supervisor
UndeÞned
Supervisor
Abort
Abort
IRQ
FIQ
--
Mode on entry