P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet - Page 75

• Manufacturer Part Number: P60ARM-B
• Description: 32-bit RISC microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

Coprocessor Interface
6.0 Coprocessor Interface
The functionality of the ARM60 instruction set may be extended by the addition of up to 16 external
coprocessors. When the coprocessor is not present, instructions intended for it will trap, and suitable
software may be installed to emulate its functions. Adding the coprocessor will then increase the system
performance in a software compatible way. Note that some coprocessor numbers have already been
assigned. Contact your supplier for up to date information.
6.1 Interface signals
Three dedicated signals control the coprocessor interface, nCPI , CPA and CPB . The CPA and CPB inputs
should be driven high except when they are being used for handshaking.
6.1.1 Coprocessor present/absent
ARM60 takes nCPI LOW whenever it starts to execute a coprocessor (or undefined) instruction. (This will
not happen if the instruction fails to be executed because of the condition codes.) Each coprocessor will have
a copy of the instruction, and can inspect the CP# field to see which coprocessor it is for. Every coprocessor
in a system must have a unique number and if that number matches the contents of the CP# field the
coprocessor should drive the CPA (coprocessor absent) line LOW. If no coprocessor has a number which
matches the CP# field, CPA and CPB will remain HIGH, and ARM60 will take the undefined instruction
trap. Otherwise ARM60 observes the CPA line going LOW, and waits until the coprocessor is not busy.
6.1.2 Busy-waiting
If CPA goes LOW, ARM60 will watch the CPB (coprocessor busy) line. Only the coprocessor which is
driving CPA LOW is allowed to drive CPB LOW, and it should do so when it is ready to complete the
instruction. ARM60 will busy-wait while CPB is HIGH, unless an enabled interrupt occurs, in which case
it will break off from the coprocessor handshake to process the interrupt. Normally ARM60 will return from
processing the interrupt to retry the coprocessor instruction.
When CPB goes LOW, the instruction continues to completion. This will involve data transfers taking place
between the coprocessor and either ARM60 or memory, except in the case of coprocessor data operations
which complete immediately the coprocessor ceases to be busy.
All three interface signals are sampled by both ARM60 and the coprocessor(s) on the rising edge of MCLK .
If all three are LOW, the instruction is committed to execution, and if transfers are involved they will start
on the next cycle. If nCPI has gone HIGH after being LOW, and before the instruction is committed, ARM60
has broken off from the busy-wait state to service an interrupt. The instruction may be restarted later, but
other coprocessor instructions may come sooner, and the instruction should be discarded.
6.1.3 Pipeline following
In order to respond correctly when a coprocessor instruction arises, each coprocessor must have a copy of
the instruction. All ARM60 instructions are fetched from memory via the main data bus, and coprocessors
are connected to this bus, so they can keep copies of all instructions as they go into the ARM60 pipeline. The
nOPC signal indicates when an instruction fetch is taking place, and MCLK gives the timing of the transfer,
so these may be used together to load an instruction pipeline within the coprocessor.
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