P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet - Page 5

• Manufacturer Part Number: P60ARM-B
• Description: 32-bit RISC microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

1.0 Introduction
The ARM60 is part of the Advanced RISC Machines (ARM) family of general purpose 32-bit
microprocessors, which offer very low power consumption and price for high performance devices. The
architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and
related decode mechanism are much simpler in comparison with microprogrammed Complex Instruction
Set Computers. This results in a high instruction throughput and impressive real-time interrupt response
from a small and cost-effective chip.
The instruction set comprises eleven basic instruction types:
¥
¥
¥
¥
The ARM instruction set is a good target for compilers of many different high-level languages. Where
required for critical code segments, assembly code programming is also straightforward, unlike some RISC
processors which depend on sophisticated compiler technology to manage complicated instruction
interdependencies.
Pipelining is employed so that all parts of the processing and memory systems can operate continuously.
Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is
being fetched from memory.
The memory interface has been designed to allow the performance potential to be realised without
incurring high costs in the memory system. Speed critical control signals are pipelined to allow system
control functions to be implemented in standard low-power logic, and these control signals facilitate the
exploitation of the fast access modes offered by industry standard dynamic RAMs.
ARM60 has a 32 bit address bus. All ARM processors share the same instruction set, and ARM60 can be
configured to use a 26 bit address bus for backwards compatibility with earlier processors.
ARM60 is a fully static CMOS implementation of the ARM which allows the clock to be stopped in any part
of the cycle with extremely low residual power consumption and no loss of state.
Notation:
0x
BOLD
binary
Two of these make use of the on-chip arithmetic logic unit, barrel shifter and multiplier to perform
high-speed operations on the data in a bank of 31 registers, each 32 bits wide;
Three classes of instruction control data transfer between memory and the registers, one optimised
for flexibility of addressing, another for rapid context switching and the third for swapping data;
Three instructions control the flow and privilege level of execution; and
Three types are dedicated to the control of external coprocessors which allow the functionality of
the instruction set to be extended off-chip in an open and uniform way.
- marks a Hexadecimal quantity
- external signals are shown in bold capital letters
- where it is not clear that a quantity is binary it is followed by the word binary
Introduction
1