P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet - Page 40

• Manufacturer Part Number: P60ARM-B
• Description: 32-bit RISC microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

P60ARM-B
4.7 Single data transfer (LDR, STR)
The instruction is only executed if the condition is true. The various conditions are defined at the beginning
of this chapter. The instruction encoding is shown in Figure 17: Single Data Transfer Instructions.
The single data transfer instructions are used to load or store single bytes or words of data. The memory
address used in the transfer is calculated by adding an offset to or subtracting an offset from a base register.
The result of this calculation may be written back into the base register if `auto-indexing' is required.
36
31
Cond
28
27
01
26
25
I
24
P U B W L
23
Figure 17: Single Data Transfer Instructions
22
21
20
19
Rn
16
15
Rd
12
Source/Destination register
Base register
Load/Store bit
Write-back bit
Byte/Word bit
Up/Down bit
Pre/Post indexing bit
Immediate offset
Condition field
11
11
11
0 = Store to memory
1 = Load from memory
0 = no write-back
1 = write address into base
0 = transfer word quantity
1 = transfer byte quantity
0 = down; subtract offset from base
1 = up; add offset to base
0 = post; add offset after transfer
1 = pre; add offset before transfer
0 = offset is an immediate value
1 = offset is a register
shift applied to Rm
Unsigned 12 bit immediate offset
Shift
Immediate offset
Offset
4
3
Offset register
Rm
0
0
0