P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet - Page 45

• Manufacturer Part Number: P60ARM-B
• Description: 32-bit RISC microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

4.8 Block data transfer (LDM, STM)
The instruction is only executed if the condition is true. The various conditions are defined at the beginning
of this chapter. The instruction encoding is shown in Figure 18: Block Data Transfer Instructions.
Block data transfer instructions are used to load (LDM) or store (STM) any subset of the currently visible
registers. They support all possible stacking modes, maintaining full or empty stacks which can grow up or
down memory, and are very efficient instructions for saving or restoring context, or for moving large blocks
of data around main memory.
4.8.1 The register list
The instruction can cause the transfer of any registers in the current bank (and non-user mode programs
can also transfer to and from the user bank, see below). The register list is a 16 bit field in the instruction,
with each bit corresponding to a register. A 1 in bit 0 of the register field will cause R0 to be transferred, a
0 will cause it not to be transferred; similarly bit 1 controls the transfer of R1, and so on.
Any subset of the registers, or all the registers, may be specified. The only restriction is that the register list
should not be empty.
Whenever R15 is stored to memory the stored value is the address of the STM instruction plus 12.
4.8.2 Addressing modes
The transfer addresses are determined by the contents of the base register (Rn), the pre/post bit (P) and the
up/down bit (U). The registers are transferred in the order lowest to highest, so R15 (if in the list) will
always be transferred last. The lowest register also gets transferred to/from the lowest memory address. By
way of illustration, consider the transfer of R1, R5 and R7 in the case where Rn=0x1000 and write back of
31
Cond
28
27
100
25
24
P U
23
Figure 18: Block Data Transfer Instructions
22
S
W L
21
20
19
Rn
16
15
Instruction Set - LDM, STM
Base register
Load/Store bit
Write-back bit
PSR & force user bit
Up/Down bit
Pre/Post indexing bit
Condition field
0 = Store to memory
1 = Load from memory
0 = no write-back
1 = write address into base
0 = do not load PSR or force user mode
1 = load PSR or force user mode
0 = down; subtract offset from base
1 = up; add offset to base
0 = post; add offset after transfer
1 = pre; add offset before transfer
Register list
41
0