P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet - Page 73

• Manufacturer Part Number: P60ARM-B
• Description: 32-bit RISC microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

Memory Interface
Address translation will normally only be necessary on an N-cycle, and this fact may be exploited to reduce
power consumption in the memory manager and avoid the translation delay at other times. The times when
translation is necessary can be deduced by keeping track of the cycle types that the processor uses.
If an N-cycle is matched to a full DRAM access, it will be longer than the minimum processor cycle time.
Stretching phase 1 rather than phase 2 will give the translation system more time to generate an abort
(which must be set up to the end of phase 1).
5.5 Locked operations
ARM60 includes a data swap (SWP) instruction that allows the contents of a memory location to be
swapped with the contents of a processor register. This instruction is implemented as an uninterruptable
pair of accesses; the first access reads the contents of the memory, and the second writes the register data to
the memory. These accesses must be treated as a contiguous operation by the memory controller to prevent
another device from changing the affected memory location before the swap is completed. ARM60 drives
the LOCK signal HIGH for the duration of the swap operation to warn the memory controller not to give
the memory to another device.
5.6 Stretching access times
All memory timing is defined by MCLK , and long access times can be accommodated by stretching this
clock. It is usual to stretch the LOW period of MCLK , as this allows the memory manager to abort the
operation if the access is eventually unsuccessful ( ABORT must be setup prior to the rising edge of MCLK
if LATEABT is LOW configuring ARM60 for early aborts).
Either MCLK can be stretched before it is applied to ARM60, or the nWAIT input can be used together with
a free-running MCLK . Taking nWAIT LOW has the same effect as stretching the LOW period of MCLK ,
and nWAIT must only change when MCLK is LOW.
ARM60 does not contain any dynamic logic which relies upon regular clocking to maintain its internal state.
Therefore there is no limit upon the maximum period for which MCLK may be stretched, or nWAIT held
LOW.
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