P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet - Page 11

• Manufacturer Part Number: P60ARM-B
• Description: 32-bit RISC microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

nRESET
nRW
nTRANS
nTRST
nWAIT
PROG32
SEQ
TCK
TDI
TDO
TMS
VDD
VSS
Name
Type
OS8
OS8
OS8
O4
IP
IP
IP
IP
P
P
I
I
I
Not reset. This is a level sensitive input signal which is used to start the processor from a
known address. A LOW level will cause the instruction being executed to terminate
abnormally. When nRESET becomes HIGH for at least one clock cycle, the processor will re-
start from address 0. nRESET must remain LOW (and nWAIT must remain HIGH) for at
least two clock cycles. During the LOW period the processor will perform dummy instruction
fetches with the address incrementing from the point where reset was activated. The address
will overflow to zero if nRESET is held beyond the maximum address limit.
Not read/write.When HIGH this signal indicates a processor write cycle; when LOW, a read
cycle. It becomes valid during phase 2 of the cycle before that to which it refers, and remains
valid to the end of phase 1 of the referenced cycle.
Not memory translate. When this signal is LOW it indicates that the processor is in user
mode. It may be used to tell memory management hardware when translation of the
addresses should be turned on, or as an indicator of non-user mode activity.
NOT Test Reset. Active-low reset signal for the boundary scan logic. This pin must be pulsed
or driven low to achieve normal device operation, in addition to the normal device reset
(nRESET). The action of this and the other four boundary scan signals are described in more
detail later in this document.
Not wait. When accessing slow peripherals, ARM60 can be made to wait for an integer
number of MCLK cycles by driving nWAIT LOW. Internally, nWAIT is ANDed with MCLK
and must only change when MCLK is LOW. If nWAIT is not used it must be tied HIGH.
32 bit Program configuration. When this signal is HIGH the processor can fetch instructions
from a 32 bit address space using address lines A[31:0] . When it is LOW the processor fetches
instructions from a 26 bit address space using A[25:0] . In this latter configuration the address
lines A[31:26] are not used for instruction fetches. Before changing PROG32 , ensure that the
processor is in a 26 bit mode, and is not about to write to an address in the range 0 to 0x1F
(inclusive) in the next cycle.
Sequential address. This output signal will become HIGH when the address of the next
memory cycle will be related to that of the last memory access. The new address will either
be the same as or 4 greater than the old one.
The signal becomes valid during phase 1 and remains so through phase 2 of the cycle before
the cycle whose address it anticipates. It may be used, in combination with the low-order
address lines, to indicate that the next cycle can use a fast memory mode (for example DRAM
page mode) and/or to bypass the address translation system.
Test Clock.
Test Data Input.
Test Data Output. Output from the boundary scan logic.
Test Mode Select.
Power supply. These connections provide power to the device.
Ground. These connections are the ground reference for all signals.
Table 1: Signal Description
Description
Signal Description
7