P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet - Page 58

• Manufacturer Part Number: P60ARM-B
• Description: 32-bit RISC microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

P60ARM-B
4.12 Coprocessor data transfers (LDC, STC)
The instruction is only executed if the condition is true. The various conditions are defined at the beginning
of this chapter. The instruction encoding is shown in Figure 26: Coprocessor Data Transfer Instructions.
This class of instruction is used to load (LDC) or store (STC) a subset of a coprocessorsÕs registers directly
to memory. ARM60 is responsible for supplying the memory address, and the coprocessor supplies or
accepts the data and controls the number of words transferred.
4.12.1 The Coprocessor Þelds
The CP# field is used to identify the coprocessor which is required to supply or accept the data, and a
coprocessor will only respond if its number matches the contents of this field.
The CRd field and the N bit contain information for the coprocessor which may be interpreted in different
ways by different coprocessors, but by convention CRd is the register to be transferred (or the first register
where more than one is to be transferred), and the N bit is used to choose one of two transfer length options.
For instance N=0 could select the transfer of a single register, and N=1 could select the transfer of all the
registers for context switching.
54
31
Cond
28
27
110
25
24
P U
23
Figure 26: Coprocessor Data Transfer Instructions
22
N
W L
21
20
19
Rn
16
15
CRd
12
Unsigned 8 bit immediate offset
Coprocessor number
Coprocessor source/destination register
Base register
Load/Store bit
Write-back bit
Transfer length
Up/Down bit
Pre/Post indexing bit
Condition field
11
0 = Store to memory
1 = Load from memory
0 = no write-back
1 = write address into base
0 = down; subtract offset from base
1 = up; add offset to base
0 = post; add offset after transfer
1 = pre; add offset before transfer
CP#
8
7
Offset
0