P60ARM-B Zarlink Semiconductor, Inc., P60ARM-B Datasheet - Page 112

• Manufacturer Part Number: P60ARM-B
• Description: 32-bit RISC microprocessor
• Manufacturer: Zarlink Semiconductor, Inc.

P60ARM-B
Note:
Note:
108
MCLK
LATEABT,
BIGEND,
DATA32,
PROG32
MCLK
nCPI
CPA, CPB
nMREQ,
SEQ
MCLK
D[31:0]
DBE
The cycle shown is a data write cycle. Here, DBE has been used to modify the behaviour of the data
bus.
Normally, nMREQ and SEQ become valid Tmsd after the falling edge of MCLK . In this cycle the
ARM has been busy-waiting, waiting for a coprocessor to complete the instruction. If CPA and CPB
change during phase 1, the timing of nMREQ and SEQ will depend on Tcpms. Most systems
should be able to generate CPA and CPB during the previous phase 2, and so the timing of nMREQ
and SEQ will always be Tmsd.
T
de
T
Figure 43: Configuration Pin Timing
dout
T
T
T
Figure 44: Coprocessor Timing
cpms
cpi
cps
Figure 42: Data Bus Control
T
dbz
T
cth
T
cph
T
dbe
T
cpih
T
cts
T
doh
T
dz