CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 127

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
19.1. Principle of Operation
19.1.1. General
The Capture Compare Module (CAPCOM, Fig. 19–1, 19–2)
contains one common free running 16bit counter (CCC) and
a number of capture and compare subunits (SU). More
details are given in Tables 19–1 and 19–2. The timer value
can be read by SW from 16bit register CCC. The CCC pro-
vides an interrupt on overflow.
Each SU is able to capture the CCC value at a point of time
given by an external input event processed by an Input
Action Logic.
A SU can also change an output line level via an Output
Action Logic at a point of time given by the CCC value.
Thus, a SU contains a 16bit capture register CCx to store the
input event CCC value, a 16bit compare register CCx to pro-
gram the Output Action CCC value, an 8bit interrupt register
CCxI and an 8bit mode register CCxM. Two types of inter-
rupts per SU enable interaction with SW.
The interrupt source output of this module is routed to the
Interrupt Controller logic. But this does not necessarily select
it as input to the Interrupt Controller. Check section “Interrupt
Controller” for the actually selectable sources and how to
select them.
For the effect of CPU clock modes on the operation of this
module refer to section “CPU and Clock System” (see
Table 4–1 on page 37).
19.1.2. Hardware Settings
The CCC0 and CCC1 clock frequency must be set via HW
option (Table 19–1 and 19–2). Some SUs use several ports.
They can be selected via HW Option Port Multiplexer (PM).
Refer to “HW Options” for setting them.
19.1.3. Initialization
After system reset the CCC and all SUs are in standby mode
(inactive).
In standby mode, the CCC is reset to value 0x0000. Capture
and compare registers CCx are reset (Comp. Reg to
0xFFFF, Capt. Reg to 0x0). No information processing will
take place, e.g. update of interrupt flags. However, the values
of registers CCxI and CCxM are only reset by system reset,
not by standby mode. Thus it is possible to program all mode
bits in standby mode and a predetermined start-up out of
standby mode is guaranteed. The flags CCxI.CAP,
CCxI.CMP and CCxI.OFL are read-only during standby
mode.
Prior to entering active mode, proper SW configuration of the
U-Ports assigned to function as Input Capture inputs and
Output Action outputs has to be made (Table 19–1, 19–2).
The Output Action ports have to be configured as special out
and the Input Capture ports as special in. Refer to “Ports” for
details.
19.1.3.1. Subunit
For a proper setup the SW has to program the following SU
control bits in registers CCxI and CCxM: Interrupt Mask
(MSK), Force Output Logic (FOL, 0 recommended), Output
Action Mode (OAM), Input Action Mode (IAM), Reset Cap-
Micronas
June 12, 2003; 6251-579-1PD
ture Register (RCR, 0 recommended), and Lock After Cap-
ture (LAC). Refer to section 19.2. for details.
Please note that the compare register CCx is reset in
standby mode. It can only be programmed in active mode.
Table 19–1: Unit 0 specific settings
Table 19–2: Unit 1 specific settings
unit
SU0
SU1
SU2
SU3
SU0,
SU1,
SU2,
SU3
unit
SU4
SU5
SU4,
SU5
Sub-
Sub-
HW Options
Item
Input
Input
Input
Output PM.
Clock
HW Options
Item
Input
Clock
PM.
PM.
PM.
PM.
Address Item
CACO
CACO
CACO
U06
C0C
Address Item
CC4I
C1C
Initialization
CC0-
OUT
CC0-IN
CC1-
OUT
CC1-IN
CC2-
OUT
CC2-IN
CC3-
OUT
CC3-IN
Initialization
CC4-
OUT
CC4-IN
CC5-
OUT
CC5-IN
CDC 32xxG-C
Setting
U3.2, U4.0
special out
U3.2, U4.1
special in
U3.1, U2.5
special out
U3.1, U2.4
special in
U3.0, U2.3
special out
U3.0, U2.2
special in
U0.5, U0.6,
U8.1
special out
U0.6
special in
Setting
U5.3, U8.0
special out
U5.3, P0.0
special in
U7.4
special out
U7.4
special in
Enable
Bit
SR0.
CCC0
Enable
Bit
SR0.
CCC1
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