CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 247

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
34. Control Register and Memory Interface
34.1. Control Register CR
When exiting Reset, the device will start up in a configuration
defined by the CR setting. For details on how to set the CR
see chapter “Core Logic”.
A full description of the functionality of all CR bits is given
below. Among others, the CR allows to configure the mem-
ory interface for connection to a variety of external memo-
ries.
The upper half word of register CR is loaded from location
0x22/0x23 only if flag EBW is at zero. If EBW is at one, the
upper half word is initialized to 0xFFFB.
STPCLK
r/w1:
r/w0:
Timers are stopped with a resolution of 1/f
RESLNG
r/w1:
r/w0:
This bit specifies the length of the reset pulse which is output
at pin RESETQ following an internal reset. If pin TEST is 1
the first reset after power on is short. The following resets are
as programmed by RESLNG. If pin TEST is 0 all resets are
long.
TSTTOG
This bit is used for test purposes only. If TSTTOG is true in IC
active mode, pin TEST2 can toggle the Multi Function pins
between Bus mode and normal mode.
EWE
r/w1:
r/w0:
This flag has to be set to allow Emu bus writes or Flash pro-
gramming (MCM). For details please refer to section “Device
Lock Module (DLM)”.
PSA
r/w1:
r/w0:
This bit allows, in EMU parts, to set the data bus access
width to ROM and Flash program storage (Table 34–2).
EB2
r/w1:
r/w0:
Micronas
r/w
r/w STPCLK RESLNG
r/w
r/w
CR
JTAG
EB2
x
7
ENDIAN
TFT
x
6
16bit access.
32bit access.
Stop Clock (Emu parts only)
Timers are stopped in debug mode.
Timers are working during debug mode.
Reset Pulse Length
Pulse length is 8/F
Pulse length is 2048/F
TEST2 Pin Toggle (Table 34–9)
Emu Bus Write Enable
Enabled (No data security).
Disabled.
Program Storage Access
External Bus Flag 2 (Table 34–1)
CE0Q and CE1Q select two external chips.
OEQ and WEQ select one external chip
connected to CE0Q (don’t use CE1Q).
For illustration see Fig. 34–13.
Value of memory location 0x20 to 0x23
TETM
Control Register
x
x
5
MAP
EB1
x
x
4
IBOOT
EBW
x
x
XTAL
3
XTAL
TSTTOG
EASY
IROM
x
2
0
.
IRAM
EWE
x
1
MFM
ICPU
June 12, 2003; 6251-579-1PD
PSA
x
0
3
2
1
0
Res
Offs
TFT
TETM
EB1
r/w1:
r/w0:
EBW
r/w1:
r/w0:
EASY
r/w1:
r/w0:
MFM
JTAG
r/w1:
r/w0
ENDIAN
r/w1:
r/w0:
Don’t change this flag dynamically
MAP
IBOOT
IROM
IRAM
ICPU
r/w1:
r/w0:
Multi Function pin Mode (Tables 34–9)
Trace Bus Full Trace (Emu parts only,
Table 34–3)
Trace Bus ETM (Emu parts only, Table 34–3)
External Bus Flag 1 (Emu/MCM parts only,
Table 34–1)
Power saving mode of memory interface.
Emu Bus configured for external Flash
memory.
Pin signals FBUSQ, BWQ0 to 3 and CE1Q
are disabled and pulled low weakly.
In CPU SLOW mode pin signal CE0Q
activates flash memory only for 1/128th of
access cycle.
Emu Bus configured for standard external
Memory. CE0Q and CE1Q always enable
memory for full access cycles.
Emu Bus Width (Emu/MCM parts only,
Tables 34–1, 34–2)
Emu Bus configured for 16bit wide external
memory. For illustration see Fig. 34–13.
Bits CR.PSA, CR.STPCLK and CR.RESLNG
are set to one and bit CR.TSTTOG is
set to zero.
Emu Bus configured for 32bit wide external
memory.
Emu Bus in Asynchronous Mode
(Table 34–1)
(Emu/MCM parts only)
Emu Bus configured for asynchronous
external memory.
Emu Bus configured for synchronous
external memory.
In synchronous mode the address bus (A) and
chip enable (CExQ) latches are transparent.
Application JTAG Interface
Enabled if TEST2 pin is high (Fig. 34–1)
Disabled
Endian setting ARM Core
Little endian.
Big endian.
Mapping (Table 34–4)
Internal Special Function ROM
(Tables 34–5, 34–8)
Internal ROM (Table 34–6)
Internal RAM (Tables 34–7, 34–8)
Internal CPU
Enable internal CPU.
Disable internal CPU
CDC 32xxG-C
245