CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 189

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
PRELIMINARY DATA SHEET
28.4. Optional Functions
The following optional functions may be designed into a cer-
tain DIGITbus implementation.
28.4.1. Abort Transmission
A master who is controlling the transmission of a telegram
can abort the sending of the address and data field. After
four T-Signs after the last bit he can send another, more
urgent telegram. If he is receiving a data field from a slave,
he must wait until the slave has finished the data field. Then
he can insert a new telegram.
28.4.2. Measure Pulse Width
The capability to measure the pulse width of a high pulse at
the DIGITbus may be used for a phase correction by some
bus nodes. The bus node who generates the bus clock,
sends a data read telegram to another bus node. The other
bus node answers with a data field which consists of a single
zero. The pulse width of this zero is measured by the master.
With this value he can calculate a phase correction value and
transmit it to this bus member, which may adjust its time slots
to the system dependencies.
28.4.3. Correct Phase
Bus nodes which does not generate the bus clock may use
the above described procedure to adjust their phase. They
have to answer to a special address with sending back a
zero. Afterwards they will receive with another special
address a correction value. With this value they can adjust
the point where they pull the bus line to modify a “T” to a one
or a zero.
28.4.4. Generate Wake-up
If the DIGITbus is passive high (no bus clock, always high
level), the clock master may be wake up by pulling the bus
level to low (dominant state) for 1/16 bit time at least. All
nodes without the clock master may be able to do that.
28.4.5. Receive Wake-up
If there is a low pulse of at least 1/64 bit time on a passive
high DIGITbus, the clock master must start to transmit the
bus clock by sending T-Signs. All Masters with a bus clock
generation unit must be able to do so in a system who uses
this feature.
28.4.6. Generate Reset
During active DIGITbus a slave may be allowed to pull down
the bus line longer than up to the end of the actual bit time (2
bit times at least). The rising edge at the end of the bit will be
delayed in this case. This will disturb the bus clock for all bus
nodes.
28.4.7. Receive Reset
The clock master is generating the rising edge at the end of a
bit time. He will detect the above described reset condition
and set a flag if the rising edge is delayed for at least 1/8 of
the bit time.
Micronas
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June 12, 2003; 6251-579-1PD