CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 78

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
or RTC values and unwanted interrupt or wake pulses.
Changing the oscillator source makes it necessary to:
1. Disable all output signals of the Power Saving Module
(ISN RTC, ISN WAPI, POL.OE=WSC.RTC=WSC.P=0).
2. Switch to the new oscillator source.
3. Initialize SSR, RTC and POL.
4. Clear WUS (WUS = 0xFFFF).
5. Clear the pending flags of the corresponding ISNs.
6. Enable the output signals and interrupts again.
7.4.3. Access to SSC and RTC
SSC and RTC are periodically altered by clock pulses. Even
if the 32kHz subsystem is clocked by the 4/5MHz oscillator, a
CPU access to SSC and RTC may be corrupted by a clock
pulse. Because this situation can’t be avoided, the SCC or
the RTC register have to be read twice. If the difference
between the two accesses is illogical, the read has to be
repeated. After a write to register RTC it has to be read and
compared to the desired value. If there is a difference, write,
read and compare have to be repeated. Since the RTC is
clocked not faster than in second distance, a read or write
access to register RTC can be done in the RTC-ISR. Such
an access is save and guarantees a correct result as long as
the RTC-ISR is finished before the next clock alters the RTC.
7.4.4. RTC Output Multiplexer
All the taps of the second, minute and hour counters are con-
nected to a multiplexer (Table 7–2) and can be selected as
output by register RTCC.SEL. The output of this multiplexer
can generate an RTC interrupt as well as a wake-up signal.
7.4.5. RTC Interrupt
Beneath above described initialization, the ICU and the cor-
responding ISN has to be initialized.
The RTC has it’s own ISN and interrupt vector thus further
investigation about the interrupt source is not necessary.
After an interrupt the flag WUS.RTC is set. The register
WUS.RTC is not necessary for, and has not to be handled by
the RTC-ISR.
7.5. Operation of Polling Module
7.5.1. Reset
The whole logic is reset by every reset, even wake-up from
power saving mode resets the Polling Module. This means,
that the logic has to be initialized after every reset.
7.5.2. Initialization and Start
The Polling Module needs the RTC Module running,
because the Polling Clock f
counter taps, and the Polling Period f
second counter taps or second counter taps. See section
7.4. for RTC Module initialization.
The enable input (POL.ENA) and the output (POL.OE) has
to be disabled.
76
PC
is derived from sub second
PP
is derived from sub
June 12, 2003; 6251-579-1PD
Precaution: Please be aware that modifying RTC or RTCC
may result in additional negative edges on RTC Out. If no
measures are taken, these edges will generate unwanted
interrupts.
It is recommended in this situation, to temporarily disable the
RTC interrupt. But, in order not to affect the intended inter-
rupts, a 1 Hz clock pulse must be avoided during modifica-
tion of RTC or RTCC.
A solution, that takes care of the above described, is reading
SSC and modifying RTC or RTCC only, if sufficient time is
available to intercept the unwanted interrupt before the next
1 Hz clock pulse occurs.
7.4.6. Inactivation
Disabling of the RTC Module can be done by selecting the
RC oscillator (OSC.SRC=2) and disabling this source
(OSC.RC=0) by simultaneously writing a one to OSC.LD.
Though selecting ground (OSC.SRC=3) would also disable
the 32kHz subsystem, this should be avoided to be compati-
ble with future extensions. Setting RTCC.SEL to zero avoids
unwanted interrupts after a non-power-on reset.
7.4.7. Signal Multiplexer
Different internal signals can be switched to SMX Out. The
internal signal can be selected via register SMX.MUX. The
possible signals are shown in table 7–6. Only the signals f
and f
used, but are intended for testing purposes.
The signal f
and calculate the corresponding reload value for the sub
second counter with external equipment.
The signal f
counter, with the help of e.g. an XTAL driven CAPCOM
counter, when driven by the internal RC oscillator.
The bypass switch (SMX.BYP) allows to bypass the SSC
and directly feed f
intended for testing purposes only and shall be written to
zero.
The port H0.2 has to be configured as normal, out, low for
operation as polling output.
Select f
output (POL.ENA, POL.OE) and load the delay counter
reload register (POL.DEL) with a non zero value.
S
are of general interest, the remaining signals may be
PC
(POL.CLK) and f
SS
S
is useful for re-adjustment of the sub second
is useful for measuring of the quartz frequency
SS
into the second counter. This feature is
PRELIMINARY DATA SHEET
PP
(POL.PER). Enable input and
Micronas
SS