CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 66

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
6.5.5. Reset Registers
This register controls the Supply and Clock Supervision
modules and allows to force a system reset.
FHR
w1:
w0:
CMA
w1:
w0:
Can be written to zero only after supply or clock supervision
reset and before first write access to register CSW1.
The Reset state in the register frame above describes the
state after a write to register CSW1.
TST
r1:
r0:
IDLE
6)
WKST
FHR
CLM
PIN
POR
6.6. Test Registers
Test registers are for manufacturing test only. They must not
be written by the user with values other than their reset val-
ues (00h). They are valid independent of the TEST input
state.
In all applications where a hardware reset may not occur
over long times, it is good practice to force a software reset
on these registers within appropriate intervals.
64
w
CSW0
CSW1
r
FHR
TST
0
7
7
-
IDLE
x
0
6
x
6
TEST is 1.
TEST is 0.
Wake Reset from WAKE or STANDBY
RESETQ Pin Reset (Tables 6–5, 6–6)
Forced Hardware Reset
Reset forced
no action
Clock and Supply Monitor Active
Both Enabled.
Both Disabled.
TEST Pin State
Wake Reset from IDLE Mode (Tables 6–5, 6–
Mode (Tables 6–5, 6–6)
Forced Hardware Reset (Tables 6–5, 6–6)
Clock Supervision Reset (Tables 6–5, 6–6)
Supply Supervision Reset (Tables 6–5, 6–6)
WKST
Clock, Supply & Watchdog Register 0
Clock, Supply & Watchdog Register 1
x
x
0
5
5
FHR
x
0
4
x
4
CLM
x
x
0
3
3
PIN
x
0
2
x
2
POR
x
x
0
1
1
WDRES
June 12, 2003; 6251-579-1PD
CMA
1
0
0
0
Res
Res
WDRES
Table 6–5: Source of last Hardware Reset (CPU Active
Modes)
Table 6–6: Source of last Hardware Reset (Power Saving
Modes)
This register controls the Watchdog module. See section
6.5.2.3. for details.
0
0
0
0
0
The flags FHR to WDRES sum up the source of all HW
resets that occurred since the last write to register CSW1.
Any write access to CSW1 resets all flags to 0.
0
0
1
w
w
CSW1
TST1
0
0
0
0
0
0
1
0
1
0
7
7
0
0
0
0
1
0
x
x
1
0
6
6
Watchdog Reset (Tables 6–5, 6–6)
0
0
1
1
0
1
1
1
Watchdog Time and Trigger Value
1
1
1
1
1
1
1
1
Clock, Supply & Watchdog Register 1
Test Register 1
1
0
5
5
For testing purposes only
0
0
0
1
0
0
x
x
1
0
4
4
PRELIMINARY DATA SHEET
0
1
0
0
0
0
x
x
Reset Source
external from RESETQ pin
internal Watchdog
internal Clock Supervision
internal Supply Supervision
internal Forced Hardware
Reset Source
external from RESETQ pin
wake-up from WAKE/STBY
wake-up from IDLE
1
0
3
3
1
0
2
2
1
0
1
1
Micronas
1
0
0
0
Res
Res