CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 89

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
11. IRQ Interrupt Controller Unit (ICU)
The Interrupt Controller Unit manages up to 63 interrupt
sources. Each interrupt source has its own interrupt vector
pointing to an interrupt service routine. One of 16 priorities
can be assigned to each channel or it can be disabled. The
Interrupt Controller Unit is connected to the nIRQ input of the
CPU.
11.1. Functional Description
Fig. 11–1:
The Interrupt Controller Unit (ICU) is composed of an Inter-
rupt Source Node (ISN) for each interrupt source, of a Prior-
ity Encoder, of a Vector Table Logic, of an Active Priority
Level Logic and a comparator (Fig. 11–1).
Each falling edge of an interrupt source signals an interrupt
request to its ISN and sets its Pending flag P (Fig. 11–2).
Besides the P flag each ISN consists of an Enable flag (E)
and a Source Priority register containing the priority of the
corresponding interrupt source. As long as both flags (E and
P) are true, the ISN outputs its priority. Otherwise it outputs
the lowest priority (that is no priority).
The Priority Encoder outputs number and priority of the ISN
with the highest active priority. If several ISNs with the same
priority are active at the same time, the ISN with the lowest
source number is selected, thus the ISNs are operated in a
HW defined order. The interrupt vector table contains the
start addresses of the interrupt service routines (ISR). The
Vector Table Base register points to the first entry of the inter-
rupt vector table. Thus the location of the interrupt vector
Micronas
E P
Priority Encoder
Address Bus
Int. Src. Node
from CPU
src prio. level
IntSrc
CRI.TE
Block Diagram
24
IntSrc
ISN
Vector Table Logic
Vect. Tab. Base
24
IntSrc
ISN
src#
prio
6
June 12, 2003; 6251-579-1PD
24
IExit
IAck
Address Bus to Mem. Ctrl.
Features
– Expanding nIRQ input of ARM7TDMI
– Up to 63 interrupt sources (39 implemented)
– 16 priority levels
– HW vectoring
– HW prioritization
– HW stacking of priority levels
– 2 cycles maximum from input to CPU nIRQ
table is programmable to any memory location. This allows
easy switching between different tables.
Fig. 11–2:
The Active Priority Level Logic outputs the priority of the cur-
rently running task (lowest priority is the background task).
The comparator activates its output if this priority is lower
than the priority output from the Priority Encoder.
DB
IntSrc
DB
IAck
src#
act. prio.
Act. Prio. Level
force prio
6
&
ISN Flags
IRQ: PC = 0x00000018
IAck <- Read from address [VTB]
IExit <- Write to address [VTB]+0x100
D Q
S
D
R
4
4
Q
LDR PC,[PC,#±<12_bit_offset>]
LDR PC,[VTB]
a
b
E
P
a>b
CDC 32xxG-C
&
CRI.GE
to Priority Encoder
src prio level
&
4
nIRQ
87