CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 183

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
Fig. 27–9:
27.3.7.3. Bus Monitor
With some Rx-All-COs it is possible to construct a user-
friendly bus monitor. The CPU has merely to observe
whether anything has been received. The contents of the CO
must be stored. The transmission time can be calculated
from the time stamp.
27.3.7.4. Maximum number of COs
The maximum number of COs depends on the size of the
CAN-RAM, the baud rate, the system clock, the BI and the
CPU accesses to the CAN-RAM.
– The BI can handle a maximum of 254 objects. The limiting
– The maximum number of COs is, of course, limited to a
Micronas
TD:
CM=Send
TD:
CM=
Rec. All
TD:
CM=
Rec. All
TD:
CM=
Rec. All
TD:
CM=
Rec. All
TD:CM = 7
factor is the 8-bit register CANxIDX in the GCS. CANxIDX
can contain 256 different values. The values 255 (empty)
and 254 (error) are reserved. The remaining values
0...253 can indicate 254 objects.
greater extent by the size of the CAN-RAM. The BI can
only access the CAN-RAM. Therefore the CA can only be
applied there.
16 bytes are reserved for each CO. One extra byte for
coding EoCA after the last CO must not be forgotten. The
CAN-RAM area after the EoCA is freely available to the
user. No EoCA is necessary if the CAN-RAM is filled com-
pletely with COs.
There is a maximum number of 32 COs possible in a
CAN-RAM of 512 bytes.
Example: CA of a BasicCAN with 4 Rx-buffers
Tx-Obj
Rx-Obj
Rx-Obj
Rx-Obj
Rx-Obj
End of Com. Area
June 12, 2003; 6251-579-1PD
– The next limiting factor can be calculated from the baud
– The value thus calculated is further limited, however, by
Max. Number CO
rate and system clock. After the BI has received an identi-
fier, it must be possible for it to scan the entire CA before
the telegram comes to an end.
t
of a minimum telegram (11 bit ID, no data), which is at the
BI’s disposal to scan the CA.
t
cess an object (A value of 6 I/O cycles is a more realistic
size than 9).
With an input frequency of 8 MHz and a baud rate (1/t
of 1 MBd, the BI could handle 24 COs. Naturally, this
value needs to be rounded off.
the CPU accesses to the CAN-RAM. Each I/O cycle
required by the CPU to write or read data in the CAN-
RAM is missing from the BI. The BI is halted by CPU
accesses. This reduces the time which the BI has to scan
the CA. Where there is a reduced CPU clock, in particular,
the user should have only limited access to the CAN-
RAM.
With the ARM CPU accessing CAN RAM, it is easy to
block the BI’s CAN-RAM access over a long time. The
ARM CPU can make a memory access with each I/O
cycle, leaving nearly no I/O cycles to the BI.
In the above example (8 MHz, 1 MBd), t
O cycles (28 * 8). The BI needs 144 I/O cycles to scan 16
COs leaving 80 I/O cycles to the CPU to process a tele-
gram. It is not necessary to process more than one tele-
gram during transmission of one telegram. As long as the
COs are managed via interrupt, 80 I/O cycles should be
more than enough to read or write a CO.
In this worst case scenario the BI needs 288 I/O cycles to
scan 32 COs. This is possible at an input frequency of 8
MHz and up to baud rate of 500 kBd. In a more realistic
estimation (average t
cycles to scan 32 COs leaving 32 I/O cycles to the CPU to
process a telegram. This means 1 MBd is possible even
with 32 COs, as long as the COs are managed via inter-
rupt only.
Due to this, care has to be taken when using free CAN-
RAM (after EoCA). It is not possible here, to make an
assumption about how many accesses a non CAN routine
makes to its data storage.
CA Scan
CO Scan
Max. Number CO
t
t
t
t
CO SCAN
CA SCAN
Bit
Q
=
=
BPR
--------------------
( 3 + TSEG1 + TSEG2 ) t
is the time from having received an ID to the end
is the worst case time needed by the BI to pro-
f
=
0
=
+
28 t
9
----
f
1
0
Bit
=
=
---------------------------------------- -
CAN RAM Size
---------------------- -
t
t
CO Scan
CO SCAN
CA SCAN
16
CDC 32xxG-C
= 6) the BI needs 192 I/O
Q
CA Scan
lasts 224 I/
181
bit
)