CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 181

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
27.3.2.9. Overwrite Mode
The BI normally processes a CO only when the transfer sta-
tus TS has been deleted; i.e. the user has processed the CO
since the last transmission. In the case of COs with which
telegrams are received, the TS flag can be by-passed. If
overwrite (OW) is permitted, the BI may overwrite a previ-
ously received telegram. When accessing data therefore, the
user always receives the most up-to-date data.
27.3.3. Interrupts
All interrupts are enabled or disabled by the global interrupt
enable flags, GTIE for Tx interrupts, GRIE for Rx interrupts
and EIE for error interrupts in the CANxCTR register. Each
error interrupt can also be masked individually in the Error
Status Mask register. A Tx interrupt can be enabled in the
corresponding CO with the Tx interrupt enable flag TIE. An
Rx interrupt can be enabled in the corresponding CO with
the Rx interrupt enable flag RIE.
An interrupt can only be initiated when the interrupt index
CANxIDX is empty (minus one). To initiate an interrupt, the
BI enters the number (0...253) of the appropriate CO in the
CANxIDX. When an error interrupt is involved, the number
254 is entered.
The BI attempts to initiate an interrupt immediately after suc-
cessful transfer. If this does not work (CANxIDX not empty),
the interrupt is pending (also error interrupt).
The BI permanently scans the CA. If, while doing so, it finds
a CO whose interrupt condition is satisfied (e.g. TIE and TS
are set), it generates an interrupt. This means that interrupts
not yet reported will not be reported in the sequence of their
occurrence, but in the sequence in which they are discovered
later.
The interrupt service routine of the user must read the
CANxIDX. The interrupt source is stored here. If CANxIDX
points to a CO (0...253), the user must reserve this. After
this, he must first delete TS so that this CO does not initiate
an interrupt again. Only then he may release CANxIDX
(CANxIDX = 255) so that the BI can enter further interrupts.
27.3.4. Rescan
The normal transmit strategy searches for the next transmit
CO in the CA. If all the transmit COs are ready to send, they
are processed one after the other. This is a democratic strat-
egy.
If higher-priority TxTgs are reported in the meantime, these
are not processed until the complete list has been finished.
With rescan, the search for Tx telegrams is started again at
the beginning of the CA. By this means the user can force
the normal strategy to be interrupted and a search to be
made first of all for higher-priority TxTgs. A transmit CO
already reported will of course be transmitted first.
The rescan requirement can be achieved dynamically, when
a transmit CO is reported, by setting the global rescan flag
GRSC.
It is also possible to configure a rescan strategy statically.
Each Tx-CO has the rescan flag RSC. If it is set, the system
starts from the beginning with the transmit search after this
CO has been processed. It is possible, for instance, to set
RSC in the low-priority Tx-COs. Each time a low-priority Tx-
CO has been handled, the search continues for higher-prior-
ity objects.
Micronas
June 12, 2003; 6251-579-1PD
The user must ensure that each Tx-CO is processed.
27.3.5. Time Stamp
The time stamp of a CO shows the user how much time has
elapsed since the transmission of the object. For this pur-
pose, he compares the time stamp with the capture timer
CANxCTIM. Because the time stamp contains the value of
the CANxCTIM at the time of the start of transmission, the
difference is proportional to the time which has elapsed.
The time stamp mechanism also enables network-wide syn-
chronization. A master transmits a Tg. All nodes note the
transmission time (local time). Then the master transmits its
own (global) transmission time. The difference between local
and global time shows by how much one’s own clock (timer)
is wrong.
27.3.6. Errors
In the error status register (CANxESTR) error messages and
status data are collected which can generate an error inter-
rupt. As long as a flag is set in the CANxESTR and not
masked in the CANxESM, the flag ERS is also set in the sta-
tus register. This means that the value 254 is written in
CANxIDX and an interrupt is generated when EIE has been
set.
An error interrupt is deleted by first deleting CANxESTR and
then releasing CANxIDX.
The 5 flags BIT, STF, CRC, FRM and ACK originate from the
protocol manager. The flag GDM (Good Morning) is not an
error flag. GDM is set when the BI is aroused from the sleep
mode by a dominant bus level.
The flag ECNT (error counter level) indicates that an error
counter has exceeded a limit value. It is set when the trans-
mit error counter exceeds the values 95, 127 and 255 or the
receive error counter exceeds the values 95 and 127.
When the BI is in the Bus-Off mode, it no longer actively par-
ticipates in the bus traffic. Nor does it receive telegrams, but
continues to observe the bus. As soon as the BI has
detected 128 x 11 successive recessive bits, it either reverts
to the error-active mode if flag BOST is zero, or it sets the
flag HLT and enters the HALT mode if flag BOST is set. At
the same time the error counters are cleared.
A Bus-Off sequence triggers two interrupts, if the error inter-
rupt is enabled. The first interrupt (ECNT=TRUE) indicates
that the transmit error counter has exceeded the value 255.
This means that the module is in the Bus-Off mode now
(BOFF=TRUE). The receive error counter is used to count
the reception of 128 x 11 successive recessive bits in the
Bus-Off mode. This is the reason for the second interrupt
(ECNT=TRUE), which indicates that the receive error
counter has exceeded the value 95 (warning level). The sec-
ond interrupt can be ignored in Bus-Off mode. The error
interrupt can be disabled during Bus-Off mode to avoid this
second interrupt.
27.3.7. Layout of the CA
The CA contains all COs beginning with the lowest identifier.
The three MSBs must be set in the byte after the last CO
(End of CA).
If the BI has received an identifier complete, it starts at the
beginning of the CA with the search for an appropriate Rx-
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