CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 53

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
A correct application program should provide a separate way
and interface to enable JTAG and to modify the Security Vec-
tor.
To allow easy JTAG access during development and debug-
ging, leave the SV not set.
5.1.1.5. ARM ID
The ARM core can contain a System Control Coprocessor
(CP15) which contains among other things an ID Register. It
5.2. I/O Map
The I/O region (Table 5–2) is divided into the lower part
(addresses 00F80000 to 0x00FBFFFF) which is connected
to the 8 bit wide bus and into the upper part (addresses
00FC0000 to 0x00FFFFFF) which is connected to the 32 bit
wide bus. Please refer to section “Register Cross Reference
Table” for detailed I/O register mapping.
Access to I/O modules which are connected to the 8 bit wide
bus is restricted: If not otherwise mentioned those modules
must be accessed by byte access only. This memory area is
organized in little endian format. If the CPU operates in big
endian format, only byte access is recommended.
Micronas
June 12, 2003; 6251-579-1PD
allows the identification of the implemented processor. There
is no CP15 implemented up to now, but the ARM ID field may
contain the same information.
5.1.1.6. Control Word
The Control Word defines the behavior of the HW during
reset. Refer to section “Core Logic” for information about
Control Word definition.
Table 5–2:
00FFFFFF
00FFFF00
00FFFEFF
00FFFE00
00FFFDFF
00FFFC00
00FFFBFF
00FC0000
00FBFFFF
00F90800
00F907FF
00F90000
00F8FFFF
00F81200
00F811FF
00F81000
00F80FFF
00F80000
Address
I/O Map
59.5k
255k
190k 8bit,
Size Access
256 32bit,
256
512
512
2k
4k
asynchronous,
no wait states
synchronous,
wait states
CDC 32xxG-C
What
IRQ and FIQ regis-
ters
DMA registers
Core registers
Free
Free
Registers
Free
CAN registers
CAN-RAM
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