CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 21

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
must be buffered by an external capacitor to AVSS. No DC
load is allowed.
VSS
The pin VSS is the negative supply terminal of the internal
digital modules (see Fig. 2–3 for external connection).
WAIT
This is the positive input to the WAIT comparator. The nega-
tive input is VREFINT. The comparator level can be adjusted
by an external voltage divider.
WAITH
This is the output of the WAIT comparator. The hysteresis
can be adjusted by an external feedback resistor to the volt-
age divider connected to the WAIT pin.
1) Trace Bus output. Active in Analyzer mode.
2) Trace Bus output. Active in ETM mode.
3) Trace Bus input. Always active.
4) Memory interface signal. Tristate if EMUTRI is high.
Please refer to section “Memory Interface” (see Table 34–1 on page 246) for details about interfaces and Trace Bus modes.
2.5. External Components
Fig. 2–3:
To provide effective decoupling and to improve EMC behav-
iour, the small decoupling capacitors must be located as
close to the supply pins as possible. The self-inductance of
these capacitors and the parasitic inductance and capaci-
tance of the interconnecting traces determine the self-reso-
Micronas
Supply
System
Ground
Resetq
+5V
+5V Supply
ESR < 14
Low ESR
4.7k
Tantal
CDC3205G-C: Recommended external supply and quartz connection.
3.3
Tantal
10
2 x 100n to 150n
47n
Ceramic
Ceramic
470n
220n
18p
18p
X7R
X7R
FVDD
FVSS
UVDD
UVDD1
UVSS
UVSS1
VDD
VSS
XTAL1
XTAL2
RESETQ
June 12, 2003; 6251-579-1PD
3.3V
5V
2.5V
5V
WEQ 4)
The output signal Write Enable connects to the external
memory’s WEQ pin and activates it for write access. Active
LOW.
WP0 to WP9
The Wake Port inputs are inputs to the Port Wake Module
inside the Power Saving Module. They serve as Wake Ports
during power saving modes and as port interrupt inputs dur-
ing CPU-active modes.
XTAL1
This is the quartz oscillator or clock input pin (see Fig. 2–3
for external connection).
XTAL2
This is the quartz oscillator output pin for two pin oscillator
circuits (see Fig. 2–3 for external connection).
nant frequency of the decoupling network. Too low a fre-
quency will reduce decoupling effectiveness, will increase
RF emissions and may adversely affect device operation.
XTAL1 and XTAL2 quartz connections are especially sensi-
tive to capacitive coupling from other pc board signals. It is
5V
2.5V
HVDD0 to 3
EVDD0 to 8
HVSS0 to 3
EVSS0 to 8
VREFINT
BVDD
AVDD
AVSS
9 x 100n to 150n
4 x 100n to 150n
10n, Ceramic
150n
Ceramic, X7R
100n to 150n
CDC 32xxG-C
3.3V/5V
Supply
System
Ground
+5V
Supply
System
Ground
Analog
Supply
Analog
Ground
19