CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 144

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
P
r1:
r0:
w1:
w0:
DMAT
r/w7-0:
22.3. Principle of Operation
The DMA Controller is operable in all CPU modes. However,
it has to be disabled (see 22.3.9.) during CPU mode switch-
ing to prevent undefined clock system behavior. For correct
CPU mode switching, follow the sequence given section 4.2.
22.3.1. Initialization of the DMA Controller
The DMA vector table has to be installed starting at a 128
byte aligned address. See figure 22–5 for DMA vector layout.
Write the start address of the DMA vector table as a 32 bit
address to the DMA Vector Base register (DVB) and note
that only bits 7 to 23 may be modified. The other bits are
forced to zero. Enable the DMA controller by setting flag DE
in the DMA Status register (DST).
The input frequency fDMA for all DMA timer can be selected
by the register DMAC in the HW Options field.
22.3.2. Initialization of a DMA Channel
All steps necessary to initialize the involved I/O module have
to be taken according to the description in the respective
chapter.
Write the appropriate values to the DMA Channel Mode reg-
ister (DCxM). Select the trigger source by field TRIG, pro-
142
r/w
r/w
DCxM
EN
P
7
x
6
DMA Timer
DMA Pending
DMA transfer pending
No DMA transfer pending
No action
Clear P
DMA timing, equation:
f
DMAT
DMAT
DMA Channel x Mode Register
x
5
=
x
4
0x0000
---------------------- -
2
DMAT
BYP
f
DMA
3
+
DIR
1
2
TRIG
1
MAS
June 12, 2003; 6251-579-1PD
0
1
0
Res
Offs
TRIG
r/w15-0:
Table 22–2:
EN
r1:
r0:
w1:
w0:
BYP
r/w1:
r/w0:
DIR
r/w1:
r/w0:
MAS
r/w3:
r/w2:
r/w1:
r/w0:
gram the DMA timer by field DMAT if necessary, select trans-
fer direction (DIR) and size (MAS) and set BYP to one.
22.3.3. Self Timed DMA Write to I/O Operation
Flag DIR in register DCxM must contain a one for writing to
an I/O module.
Write the source address (24 bit), pointing to the first plus
one element, and the block size (8 bit) to the corresponding
DMA vector table entry.
Start the DMA sequence by writing the first element to be
transferred to the data register of the corresponding I/O mod-
ule and enable the DMA channel.
22.3.4. Self Timed DMA Read from I/O Operation
Flag DIR in register DCxM must contain a zero for reading
from an I/O module.
Write the destination address (24 bit), pointing to the first ele-
ment, and the block size (8 bit) to the corresponding DMA
vector table entry.
TRIG
3
x
x
x
x
2
x
x
x
x
1
0
0
1
1
Trigger Source
(see Table 22–2)
Enable DMA channel
DMA sequence active
DMA sequence finished
enable DMA channel
disable DMA channel
Bypass Interrupt
don’t bypass DMA-Request to ICU
bypass DMA-Request to ICU.
DMA Direction
write to I/O-module
read from I/O-module
Memory Access Size
reserved
32-bit (not supported)
16-bit (not supported)
DMA Trigger Sources
8-bit
0
0
1
0
1
Source
DMA request from I/O-module
DMATx
PINT0
PINT1
PRELIMINARY DATA SHEET
Micronas