CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 52

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

CDC 32xxG-C
5.1. RAM and ROM
On-chip RAM is composed of static RAM cells. It is protected
against disturbances during reset as long as the specified
operating voltages are available.
The 128PQFP Multi Chip Module also contains a 512K byte
Flash EEPROM of the AMD Am29LV400BT type (top boot
configuration). This device exhibits electrical byte program
and sector erase functions. Refer to the AMD data sheet for
details.
Future mask ROM derivatives may be specified to contain
less or more internal RAM and ROM than this IC:
– ROM will grow upward from 0x0200000 to 0x09FFFFF
– RAM will always grow upward from physical address
– SFR will grow upward from physical address 0x0F00000
– The I/O area will grow upward from physical address
Mirrored means the memory is accessible at both locations.
Remapped means the memory is accessible at the new loca-
tion only.
All parts (ROM, Flash and EMU) contain at least the I/O
area, the RAM and the SFR.
5.1.1. Reserved Addresses
Reserved Addresses (Table 5–1) are memory locations
which define the behavior of internal HW or external sys-
tems. In our system the memory locations at address 0 and
following have dedicated functions. The function of these
memory locations depend on which kind of physical memory
is mapped to these locations. As you can see in Fig. 5–1,
ROM/Flash or SFR is mapped to location 0 at reset. Thus, a
meaningful Control Word and reset vector can be fetched at
start-up..
5.1.1.1. HW Options
Please refer to section “Hardware Options” for information
about layout of the HW Options field and the corresponding
Registers in the I/O area. To activate the HW Options related
functions, the SW has to copy them to the corresponding
locations in the I/O area.
But nevertheless these are HW Options. It is not possible to
modify them by SW in future ROM parts.
5.1.1.2. ROM ID
The ROM ID serves as identification of the corresponding
application/SFR program. It will be read by an external sys-
tem (test, debug) and doesn’t influence internal HW.
The ROM ID contains a half-word sized hexadecimal value.
The range is 0x0000 to 0xFFFF.
50
(8MByte) and can be remapped to physical address 0
(growing upward to 0x07FFFFF). It is 16bit wide and is
asynchronously accessed with wait states.
0x0C00000 to 0x0DFFFFF (2MByte) and can be mirrored
to physical address 0. It is 32bit wide and is asynchro-
nously accessed without wait states.
to 0x0F7FFFF (0.5MByte) and can be mirrored to physical
address 0.
0x0F80000 to 0x0FFFFFF (0.5MByte). It is 16bit wide and
is asynchronously accessed with wait states.
June 12, 2003; 6251-579-1PD
Table 5–1: Reserved Addresses
5.1.1.3. Factory ID
The Factory ID contains a factory defined code. It holds infor-
mation about the HW version and other items. It can be read
by an external system (test, debug) and doesn’t influence
internal HW. The SFR system may use this information and
adapt its behavior according to the Factory ID. The layout of
the Factory ID is not yet defined.
5.1.1.4. Security Vector (SV)
If the Security Vector is set (equal to 0x55AA55AA), the SFR
does not enable the JTAG interface. In this way the applica-
tion program may keep JTAG access disabled.
An empty (erased) Flash ROM contains all ones. Hence the
JTAG access is enabled.
Keep the following sequence to reprogram a Flash ROM:
1. Clear the SV (i.e. program the SV address with
0x00000000 or any other value different from 0x55AA55AA).
2. Erase the Flash ROM (this sets the SV to 0xFFFFFFFF).
3. Program all of the Flash ROM, but skip the SV address
(leave it at 0x0xFFFFFFFF).
4. Verify the Flash ROM.
5. If ok, set the SV (write 0x55AA55AA to the SV address).
Otherwise return to step 2.
This procedure guarantees that the JTAG interface will be
enabled after reset via SFR, if something went wrong during
Flash ROM programming.
Address
030 - 5F
02C - 2F
02A - 2B
028 - 29
024 - 27
020 - 23
01C - 1F
018 - 1B
014 - 17
010 - 13
00C - 0F
008 - 0B
004 - 07
000 - 03
Size
[byte]
48
4
2
2
4
4
4
4
4
4
4
4
4
4
Usage if mapped/mirrored to 0
RAM
General
purpose
RAM. No
HW
defined
action.
FIQ (Fast Interrupt)
IRQ (Interrupt)
Reserved
Data Abort
Prefetch Abort
SWI (Software Interrupt)
Undefined instruction
Reset
PRELIMINARY DATA SHEET
ROM/
Flash
HW Options
Factory ID
reserved
ROM ID
Security
Vector
Control word
SFR
ARM ID
Micronas