CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 87

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
10. Memory Patch Module V1.0
The Memory Patch Module allows the user to modify data
words within the ROM/Flash address space without to
change the contents of the ROM/Flash itself. This function is
useful if faulty parts of software or data are detected after the
ROM code has been cast into mask ROM.
An application software in ROM has to be prepared to sup-
port patching. It loads addresses and code or data e.g. from
external non-volatile memory to program the appropriate
registers of the module. After this kind of Patch Module ini-
tialization, code and / or data of the specified address loca-
tions will become replaced by the contents of the Patch Data
Registers upon address matches.
Fig. 10–1:
10.1. Principle of operation
10.1.1. General
The logic contains up to ten patch cells (see Fig. 10–1 on
page 85), each consisting of a 21 bit compare register (Patch
Address Register, PAR), a 21 bit address comparator, a
Patch Select bit (PSELx) in the Patch Enable Register (PER)
and a 32bit Patch Data Register (PDR).
The current address information for a ROM access is fed to a
bank of patch cells. In case of a match in one patch cell, and
provided that the corresponding Patch Enable Register bit is
set, the module’s logic disables the ROM data bus drivers
and instead places the data information from the correspond-
ing Patch Data Register on the data bus.
Micronas
8 bit
I/O bus
1)
i. e. patched ROM addr. 0x0000.0348
is 0x0020.0348 with CR.MAP = 00.
A<22:2>
Addresses refer to ROM base addr.,
1)
Block Diagram
21
Patch Cell x
8
PAR
PSELx
21
PMEN
&
&
32
from
Memory
Controller
PDR
from
other
patch
cells
June 12, 2003; 6251-579-1PD
predecrom
1
Single ROM locations are replaced directly. Longer e. g.
faulty code sequences may be bypassed by introducing a
jump to a code sequence or a call of a subroutine in RAM.
The program part in RAM ends with a return or jump to the
appropriate address in ROM. With it even complex software
parts may be replaced.
Features
– patching of up to 10 different (32bit) words in ROM
10.1.2. Initialization
After reset bit PER.PMEN is reset to 0 and patch operation is
disabled. All patch cell registers are in write mode and may
be programmed.
At first, select a cell by setting the corresponding PSELx bit
in register PER (PSELx = 1). Then feed the address into reg-
ister PAR and the accessory 32bit patch data into register
PDR.
If desired, repeat the above sequence for further patch cells.
Be shure to have only one PSELx bit set at a time, although
more than one register may be selected and programmed
with a single access. This is possible because of used sub-
addressing for the address and data registers, but probably
of very rarely use indeed.
read
address space
from
other
patch
cells
&
Timing
Patch
Logic
PATOE
&
f
ROM enable
BUS
CDC 32xxG-C
32
data bus
85