CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 199

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
full. In this case, the FIFO is frozen, but the shift register con-
tinues operation. The flag RDL indicates the latter case.
If the shift register is stored to the receive FIFO because a T
sign was received, the corresponding flag EOFLD is set, indi-
cating that this is the last entry of a field.
The corresponding flag FTYP is modified at the same time. If
two or more consecutive T signs were received in front of the
actual field, it is set, indicating that this field has to be inter-
preted as an address field. If only one T sign has been
received in front of the actual field, it is cleared, indicating
that it has to be interpreted as a data field.
The flag TGV is set if two consecutive T-signs were received.
This is the moment to read status flags and Receive FIFO.
The flags PV and ERR have to be interpreted. Even if an
error occurred, the Receive FIFO must be emptied by read-
ing it because every telegram or fragment is stored there.
Otherwise reception of the next telegram may overflow the
receive FIFO, which is indicated by flag RDL.
Every time you want to read DGRTMA, it is ingenious to read
DGRTMD first, because DGRTMD and DGRTMA are over-
written with a read access to DGRTMA.
29.4.5.1. Receive FIFO
The receive FIFO contains entries as long as flag NEM is
true.
Short telegrams can be buffered completely in the receive
FIFO. SW must buffer long telegrams and read parts of it in
time.
29.4.6. Sleep Mode
Only the receive bit logic is active in sleep mode. Neither
transmission nor reception of telegrams is possible.
A wake-up (passive high to low edge) is signaled by flag PV.
The DIGITbus master is not automatically activated by a
wake-up. This has to be done by SW. The flag PV can be
used to trigger an interrupt.
Switching to Sleep Mode while a telegram is transmitted can
cause problems. Hence make sure, that bus clock generation
is switched off only if bus is idle (T-signs).
29.4.7. Abort Transmission
Writing a one to flag FLUSH aborts the transmission of a
telegram after completion of the actual transmitted bit, if the
DIGITbus master is the transmitter. The transmit FIFO is
emptied and another, more urgent telegram can be transmit-
ted. Transmission of the new telegram starts, as soon as 4
consecutive T signs were received after the aborted tele-
gram.
Flag TGV is cleared with a FLUSH. This is the reason why
TGV is set (and interrupt is triggered if enabled) after recep-
tion of 2 T signs, even if no telegram was aborted by FLUSH
because it happened during transmission of T signs.
Resetting of Flag TGV is the reason why an aborted address
field is marked as data field (FTYP = 0) in the RxFIFO.
It is not possible to abort a telegram or a field which is trans-
mitted by another bus node.
Micronas
June 12, 2003; 6251-579-1PD
29.4.8. Interrupt
Five flags (RDL, NEM, NOF, TGV, PV) are connected to the
interrupt source output by an or operation. This output can
be enabled globally by flag INTE. The interrupt generation of
two flags (NEM, NOF) can be enabled locally by flags ENEM
and ENOF. A rising edge of a flag triggers the interrupt
source output.
Fig. 29–7:
29.4.9. Measure Pulse Width
The pulse width (high time) of every non T sign is stored with
the falling edge of the bus signal in status register DGS1TA
in the field PW. T signs doesn’t affect PW. It must be read
before the falling edge of the next non T sign.
29.4.10. Correct Phase
The rising edge of the bus signal can be delayed by inner
(sampling and filter) or outer (bus load) influences. This
delayed rising edge resets a 6 bit transmit counter in the
transmit bit logic. The transmit counter pushes the bus line
low when it reaches 15 (transmitting 0) or 31 (transmitting 1).
It releases the bus line when it reaches 55.
The transmit counter is reset to a value which contains two
zeros at the most significant position and the four PHASE
bits of the control register DGC1 at the least significant posi-
tion. This allows an adjustment of the transmitted non T
signs between 0 and 15/64 of the whole bit length.
29.4.11. Error
The setting of flag ERR may have one of the following
causes:
– Wrong baud rate of DIGITbus Master or other bus nodes.
– Wrong port configuration of DIGITbus Master.
– Disturbances on bus line.
– HW damaged of DIGITbus Master.
29.4.12. Precautions
Don’t access DIGITbus registers in CPU Slow and Deep
Slow mode. This can cause interrupts.
If f
mode possible (Table 29–2).
INTE
RDL
ENEM
NEM
ENOF
NOF
TGV
PV
XTAL
is 5 MHz, a bus clock of 31.25 kHz is only in PLL
Interrupt Sources
&
&
CDC 32xxG-C
OR
&
DIGITbus
Interrupt
Source
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