CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 45

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
4.5. EMI Reduction Module (ERM)
The IC contains an EMI Reduction Module (ERM), which is
capable of reducing electromagnetic radiation that might
cause interference to other electronic equipment. The con-
cept of this circuit uses precisely defined time offsets of the
master clock phases as generated by the PLL. Thus, the
module is only available in PLL modes.
All internal clock signals except f
the sampling time points of clocked inputs and outputs of all
internal modules are modulated. To avoid a possible perfor-
mance degradation of, e.g., communication modules in a
user environment, the maximum possible delay of the sam-
pling clock phase can be controlled with the parameters
given in table 4–6. In critical applications, I/O sampling time
point modulation and EMI reduction can thus be compro-
mised. Section 4.7. gives application hints.
Features
– Strong suppression of electromagnetic radiation
– Precisely controlled effect on sampling time points of
– All parameters fully controllable and reproducible
– Three operation modes for different purposes
– Works for clock frequencies of up to 48 MHz
– No degradation of CPU performance
4.5.1. Modes
The ERM has 4 modes of operation:
– Mode 0, ERM off.
– Mode 1 is intended for the low f
– Mode 2. This mode is primarily intended for the deactiva-
– Mode 3 gives best results at medium and high f
In each of the three operation modes the parameters may be
particularly chosen with the help of registers ERMC.SUP and
ERMC.TOL, to achieve an optimum suppression while keep-
ing phase modulation of f
three sets of parameters with maximum f
of:
–
–
–
are given as examples. However, other individual settings
are possible (see section 4.5.2.).
At f
suppression is possible. At an f
be switched off (mode 0).
Micronas
clocked I/O (ADC, CAN, UART, SPI etc.)
or 10 MHz with a clock multiplier of n = 2
(PLLC.PMF = 1).
Mode 1 with a clock tolerance of 7 has a similar harmon-
ics suppression as the formerly used EMI Reduction Mod-
ule V3.1.
tion process of mode 3 but may also be used for opera-
tion. It performs best at high clock frequencies.
quencies. At medium frequencies it is even capable of a
certain suppression of the fundamental.
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7.5 ns (weak),
12.5 ns (normal) and
20 ns (strong)
frequencies of 40 MHz and above only a limited EMI
IO
as low as possible. In Table 4–6,
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XTAL
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of 50 MHz the ERM must
are affected. Thus also
frequencies of 8 MHz
IO
sampling delays
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June 12, 2003; 6251-579-1PD
fre-
4.5.2. Rules for Setting Parameters
Each f
parameters. For individual settings other than those given in
Table 4–6 the rules are given below.
For mode 1 the limits are:
– The suppression strength has no effect and should be
– The clock tolerance must not exceed the values given in
For modes 2 and 3 the limits are:
– Numbers must not exceed the values given in the col-
– The clock tolerance must be equal to or less than (sup-
– In mode 2 the suppression strength must not exceed 43.
– In mode 3 the sum of clock tolerance and suppression
4.5.3. Initialization
For operation of the ERM, the clock system has to be in one
of the PLL modes. After Reset, the ERM is in mode 0. All
internal registers are reset to their default values. Registers
TOL, SUP and EOM are also reset by PLLC.PMF=0.
The initialization must be done in the following order:
1. Set the clock tolerance (ERMC.TOL) to 1. Set the sup-
pression strength (ERMC.SUP) to 1 (modes 2 and 3 only).
2. Select the desired mode (1...3) in ERMC.EOM according
to Table 4–6 (steps 1. and 2. must not be done in one opera-
tion).
3. Select the desired suppression strength (ERMC.SUP).
4. Select the desired clock tolerance (ERMC.TOL).
4.5.4. Deactivation
To deactivate the ERM, the following sequence must be
observed:
1. If in mode 3, enter mode 2 by writing 2 to field
ERMC.EOM.
2. Set the clock tolerance parameter (ERMC.TOL) to 1
(steps 1. and 2. must not be done in one operation).
3. Set the suppression strength (ERMC.SUP) to 1 (modes 2
and 3 only).
4. Wait at least 8 f
ing the In-Phase flag ERMC.INPH.
5. Wait for flag ERMC.INPH to be set (may take up to 80 f
cycles), then clear the field ERMC.EOM to return to mode 0.
This will turn off the ERM.
6. To reset the ERM, set SUP=TOL=0 (same result achieved
by setting PLLC.PMF=0 when back in FAST mode).
kept at 0.
the columns for strong settings.
umns for strong settings.
pression strength +1)/2.
strength must not exceed 43.
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multiplier n and each mode requires its own set of
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cycles (e.g. CPU NOPs) before check-
CDC 32xxG-C
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43