CDC3205G-C Micronas, CDC3205G-C Datasheet - Page 75

• Manufacturer Part Number: CDC3205G-C
• Description: Automotive Controller Family The Device is a Microcontroller For Use in Automotive Applications.the On-chip Cpu is an Arm Processor ARM7TDMI with 32-bit Data And Address Bus, Which Supports Thumb format Instructions.
• Manufacturer: Micronas

PRELIMINARY DATA SHEET
7.3. Operation of Power Saving Module
Before entering a power saving mode, the necessary wake-
up sources have to be configured carefully. The reset/wake-
up reason in register CSW1 and the wake-up source register
WUS have to be cleared. Please see section “CPU and
Clock System” for information about entering a power saving
mode.
7.3.1. Configuration of Wake Sources
7.3.1.1. Port Wake Module
If an external event driven wake-up is necessary, the Port
Wake Module has to be configured according to section 7.6.
The register WUS has to be cleared. Flag WSC.P has to be
set, enabling the Port Wake Module output signal to gener-
ate a wake-up signal by setting signal WAKE_RES.
If a Wake Port shall be operated in polling mode (level trig-
gered), configuration of RTC Module and Polling Module is
necessary as described in sections 7.4. and 7.5.
7.3.1.2. RTC Module
If a cyclic wake-up is necessary, the RTC Module has to be
configured according to section 7.4. Flag WUS.RTC has to
be cleared. Flag WSC.RTC has to be set, enabling the
WUS.RTC output signal to generate a wake-up signal by set-
ting signal WAKE_RES.
7.3.2. Configuration of Interrupts
During CPU active modes, the RTC Module and the Port
Wake Module can be operated as interrupt sources. The ICU
and the corresponding ISNs have to be configured according
to section “IRQ Interrupt Controller Unit”.
7.3.3. WAKE/STANDBY
With writing WAKE/STBY to SR1.CPUM, the VDD regulator
is immediately switched off and a core and a port reset signal
is generated.
A wake-up signal sets WAKE_RES to one, immediately pull-
ing pin RESETQ to low. This sets register SR1.CPUM to
FAST, disabling the WAKE_RES output of the Power Saving
Module and enables the VDD generator. When VDD is active
again, the signal CLS is cleared and the reset extension is
started. After the reset extension has finished, the pin
RESETQ is released and the core and port reset signals
(RES_5, RESPORT, RESCORE) are pulled low. The flag
CSW1.WKST is set.
The CPU starts execution at the reset vector and can read
the reset/wake-up reason in register CSW1. The wake-up
source can be read in register WUS and should be cleared
thereafter, otherwise Wake Port interrupts are not possible.
7.3.4. IDLE
With writing IDLE to SR1.CPUM, the VDD regulator is imme-
diately switched off, the auxiliary VDD generator is switched
on and a core reset signal is generated.
A wake-up signal sets WAKE_RES to one, immediately pull-
ing pin RESETQ to low. This sets register SR1.CPUM to
FAST, disabling the WAKE_RES output of the Power Saving
Module and enables the VDD generator and disables the
Micronas
June 12, 2003; 6251-579-1PD
auxiliary VDD generator. When VDD is active again, the sig-
nal CLS is cleared and the reset extension is started. After
the reset extension has finished, the pin RESETQ is
released and the core reset signal is pulled to low. The flag
CSW1.IDLE is set.
The CPU starts execution at the reset vector and can read
the reset/wake-up reason in register CSW1. The wake-up
source can be read in register WUS and should be cleared
thereafter, otherwise Wake Port interrupts are not possible.
7.3.5. Precautions
The SW has to guarantee the ability of wake-up by careful
configuration of the wake logic.
Especially the necessary Wake Ports have to be configured
as input. Verifying the necessary configuration before switch-
ing to a power saving mode will enhance the safety.
Enabling wake-up by pin only is dangerous. Accidentally
entering a power saving mode or if a flag is modified by elec-
trical over stress (EOS) in a power saving mode, may lead to
an IC which can’t be wakened.
From an inadvertently entered power saving mode, with no
wake source being enabled, neither the watchdog nor the
clock supervision nor any other internal reset source, but
only an external reset on pin RESETQ may recover the
device.
Because neither the VBG generator nor the RESET compar-
ator are enabled during power saving modes, proper CMOS
input levels (V
required on pin RESETQ during a wake-up reset. The exter-
nal circuitry must allow the device to establish WRV
pin.
The specified power saving mode current consumption val-
ues are only obtainable when CMOS input levels
(V
– in IDLE mode all H-, P- and U-Ports
– in WAKE/STANDBY modes all, not only the configured,
If an RTC-/Polling module is not used, it is advisable to
switch it off to reduce current consumption. Its outputs
should be disabled.
il
Wake Ports.
=xV
SS
0.3V and V
il
=UV
ih
SS
=xV
0.3V and V
DD
0.3V) are applied to:
CDC 32xxG-C
ih
=UV
DD
0.3V) are
il
on that
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