UPSD3234AV-24U1T STMicroelectronics, UPSD3234AV-24U1T Datasheet - Page 108

• Manufacturer Part Number: UPSD3234AV-24U1T
• Description: Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM
• Manufacturer: STMicroelectronics

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uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
Reset Flash. The Reset Flash instruction con-
sists
85., page
by the standard two WRITE decoding cycles (writ-
ing AAh to 555h and 55h to AAAh). It must be ex-
ecuted after:
–
–
The Reset Flash instruction puts the Flash memo-
ry back into normal READ Mode. If an Error condi-
tion has occurred (and the device has set the Error
Flag Bit (DQ5) to '1' the Flash memory is put back
into normal READ Mode within 25 s of the Reset
Flash instruction having been issued. The Reset
Flash instruction is ignored when it is issued dur-
ing a Program or Bulk Erase cycle of the Flash
memory. The Reset Flash instruction aborts any
on-going Sector Erase cycle, and returns the
Flash memory to the normal READ Mode within
25 s.
Reset (RESET) Signal. A pulse on Reset (RE-
SET) aborts any cycle that is in progress, and re-
sets the Flash memory to the READ Mode. When
the reset occurs during a Program or Erase cycle,
the Flash memory takes up to 25 s to return to the
READ Mode. It is recommended that the Reset
(RESET) pulse (except for Power-on RESET, as
described in
TUS AT RESET, page
that the Flash memory is always ready for the
MCU to retreive the bootstrap instructions after the
reset cycle is complete.
SRAM
The SRAM is enabled when SRAM Select (RS0)
from the DPLD is High. SRAM Select (RS0) can
contain up to two product terms, allowing flexible
memory mapping.
The SRAM can be backed up using an external
battery. The external battery should be connected
108/170
Reading the Flash Protection Status or Flash
ID
An Error condition has occurred (and the
device has set the Error Flag Bit (DQ5) to '1'
during a Flash memory Program or Erase
cycle.
of
101). It can also be optionally preceded
one
RESET TIMING AND DEVICE STA-
WRITE
132) be at least 25 s so
cycle
(see
Table
to Voltage Stand-by (V
external battery connected to the uPSD3200, the
contents of the SRAM are retained in the event of
a power loss. The contents of the SRAM are re-
tained so long as the battery voltage remains at 2V
or greater. If the supply voltage falls below the bat-
tery voltage, an internal power switch-over to the
battery occurs.
PC4 can be configured as an output that indicates
when power is being drawn from the external bat-
tery. Battery-on Indicator (V
with the supply voltage falls below the battery volt-
age and the battery on Voltage Stand-by (V
PC2) is supplying power to the internal SRAM.
SRAM Select (RS0), Voltage Stand-by (V
PC2) and Battery-on Indicator (V
all configured using PSDsoft Express Configura-
tion.
Sector Select and SRAM Select
Sector Select (FS0-FS7, CSBOOT0-CSBOOT3)
and SRAM Select (RS0) are all outputs of the
DPLD. They are setup by writing equations for
them in PSDsoft Express. The following rules ap-
ply to the equations for these signals:
1. Primary Flash memory and secondary Flash
2. Any primary Flash memory sector must not be
3. A secondary Flash memory sector must not be
4. SRAM, I/O, and Peripheral I/O spaces must
5. A secondary Flash memory sector may
6. SRAM, I/O, and Peripheral I/O spaces may
memory Sector Select signals must not be
larger than the physical sector size.
mapped in the same memory space as
another Flash memory sector.
mapped in the same memory space as
another secondary Flash memory sector.
not overlap.
overlap a primary Flash memory sector. In
case of overlap, priority is given to the
secondary Flash memory sector.
overlap any other memory sector. Priority is
given to the SRAM, I/O, or Peripheral I/O.
STBY
, PC2). If you have an
BATON
BATON
, PC4) is High
, PC4) are
STBY
STBY
,
,