UPSD3234AV-24U1T STMicroelectronics, UPSD3234AV-24U1T Datasheet - Page 54

• Manufacturer Part Number: UPSD3234AV-24U1T
• Description: Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM
• Manufacturer: STMicroelectronics

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uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
Table 41. Description of the T2CON Bits
Note: 1. The RCLK1 and TCLK1 Bits in the PCON Register control UART 2, and have the same function as RCLK and TCLK.
Table 42. Timer/Counter2 Operating Modes
Note:
54/170
Baud Rate
Generator
Capture
reload
Mode
16-bit
16-bit
Auto-
Off
Bit
7
6
5
4
3
2
1
0
= falling edge
RxCLK
TxCLK
or
0
0
0
0
0
0
1
1
x
Symbol
RCLK
TCLK
CP/RL2
EXEN2
EXF2
C/T2
TR2
TF2
T2CON
(1)
(1)
RL2
CP/
0
0
0
0
1
1
x
x
x
Timer 2 overflow flag. Set by a Timer 2 overflow, and must be cleared by software. TF2
will not be set when either (RCLK, RCLK1)=1 or (TCLK, TCLK)=1
Timer 2 external flag set when either a capture or reload is caused by a negative
transition on T2EX and EXEN2=1. When Timer 2 Interrupt is enabled, EXF2=1 will
cause the CPU to vector to the Timer 2 Interrupt routine. EXF2 must be cleared by
software
Receive clock flag (UART 1). When set, causes the serial port to use Timer 2 overflow
pulses for its receive clock in Modes 1 and 3. TCLK=0 causes Timer 1 overflow to be
used for the receive clock
Transmit clock flag (UART 1). When set, causes the serial port to use Timer 2 overflow
pulses for its transmit clock in Modes 1 and 3. TCLK=0 causes Timer 1 overflow to be
used for the transmit clock
Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of
a negative transition on T2EX if Timer 2 is not being used to clock the serial port.
EXEN2=0 causes Time 2 to ignore events at T2EX
Start/stop control for Timer 2. A logic 1 starts the timer
Timer or Counter select for Timer 2. Cleared for timer operation (input from internal
system clock, t
Capture/reload flag. When set, capture will occur on negative transition of T2EX if
EXEN2=1. When cleared, auto-reload will occur either with TImer 2 overflows, or
negative transitions of T2EX when EXEN2=1. When either (RCLK, RCLK1)=1 or (TCLK,
TCLK)=1, this bit is ignored, and timer is forced to auto-reload on Timer 2 overflow
TR2
1
1
1
1
1
1
1
1
0
T2MOD
DECN
0
0
1
1
x
x
x
x
x
CPU
); set for external event counter operation (negative edge triggered)
T2CON
EXEN
0
1
x
x
0
1
0
1
x
T2EX
P1.1
x
0
1
x
x
x
reload upon overflow
reload trigger (falling edge)
Down counting
Up counting
16-bit Timer/Counter
(only up counting)
Capture (TH1,TL2)
(RCAP2H,RCAP2L)
No overflow interrupt
request (TF2)
Extra External Interrupt
(Timer 2)
Timer 2 stops
Function
Remarks
Internal
f
f
f
OSC
OSC
OSC
—
Input Clock
/12
/12
/12
(P1.0/T2)
External
f
f
f
OSC
OSC
OSC
MAX
MAX
MAX
—
/24
/24
/24