UPSD3234AV-24U1T STMicroelectronics, UPSD3234AV-24U1T Datasheet - Page 71

• Manufacturer Part Number: UPSD3234AV-24U1T
• Description: Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM
• Manufacturer: STMicroelectronics

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I
There are two serial I
uPSD323X Devices.
The serial port supports the twin line I
sists of a data line (SDAx) and a clock line (SCLx).
Depending on the configuration, the SDA and SCL
lines may require pull-up resistors.
In both I
I/O port lines as follows.
The system is unique because data transport,
clock generation, address recognition and bus
control arbitration are all controlled by hardware.
Figure 39. Block Diagram of the I
Table 50. Serial Control Register (SxCON: S1CON, S2CON)
2
C INTERFACE
SDA1, SCL1: the serial port line for DDC
Protocol
SDA2, SCL2: the serial port line for general
I
SDA1 / P4.0, SCL1 / P4.1, SDA2 / P3.6, SCL2
/ P3.7
CR2
2
C bus connection
7
2
C interfaces, these lines also function as
ENII
6
SCLx
SDAx
2
C ports implemented in the
Arbitration and Sync. Logic
STA
5
2
C Bus Serial I/O
2
C-bus, con-
uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
7
7
7
7
STO
4
Bus Clock Generator
Control Register
Status Register
Slave Address
Shift Register
The I
handling and operates in 4 modes.
These functions are controlled by the SFRs.
ADDR
3
Master transmitter
Master receiver
Slave transmitter
Slave receiver
SxCON: the control of byte handling and the
operation of 4 mode.
SxSTA: the contents of its register may also
be used as a vector to various service
routines.
SxDAT: data shift register.
SxADR: slave address register. Slave address
recognition is performed by On-Chip H/W.
2
C serial I/O has complete autonomy in byte
0
0
0
0
AA
2
CR1
1
AI06649
CR0
0
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