UPSD3234AV-24U1T STMicroelectronics, UPSD3234AV-24U1T Datasheet - Page 126

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UPSD3234AV-24U1T

Manufacturer Part Number
UPSD3234AV-24U1T
Description
Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM
Manufacturer
STMicroelectronics
Datasheet
www.DataSheet4U.com
uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
Port D – Functionality and Structure
Port D has two I/O pins (only one pin, PD1, in the
52-pin package). See Figure
68., page
Out Mode, and therefore no Control Register is re-
quired. Of the eight bits in the Port D registers,
only Bits 2 and 1 are used to configure pins PD2
and PD1.
Port D can be configured to perform one or more
of the following functions:
Figure 67. Port D Structure
126/170
MCU I/O Mode
CPLD Output – External Chip Select (ECS1-
ECS2)
127. This port does not support Address
ECS [ 2:1 ]
WR
WR
READ MUX
DATA OUT
DIR REG.
D
D
REG.
P
D
B
67
Q
Q
and
Figure
DATA OUT
DATA IN
Port D pins can be configured in PSDsoft Express
as input pins for other dedicated functions:
CPLD Input – direct input to the CPLD, no
Input Macrocells (IMC)
Slew rate – pins can be set up for fast slew
rate
CLKIN (PD1) as input to the macrocells flip-
flops and APD counter
PSD Chip Select Input (CSI, PD2). Driving this
signal High disables the Flash memory, SRAM
and CSIOP.
CPLD- INPUT
OUTPUT
OUTPUT
SELECT
MUX
ENABLE PRODUCT
TERM (.OE)
PORT D PIN
AI06606

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