UPSD3234AV-24U1T STMicroelectronics, UPSD3234AV-24U1T Datasheet - Page 119

• Manufacturer Part Number: UPSD3234AV-24U1T
• Description: Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM
• Manufacturer: STMicroelectronics

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I/O PORTS (PSD MODULE)
There are four programmable I/O ports: Ports A, B,
C, and D in the PSD Module. Each of the ports is
eight bits except Port D, which is 3 bits. Each port
pin is individually user configurable, thus allowing
multiple functions per port. The ports are config-
ured using PSDsoft Express Configuration or by
the MCU writing to on-chip registers in the CSIOP
space. Port A is not available in the 52-pin pack-
age.
The topics discussed in this section are:
General Port Architecture
The general architecture of the I/O Port block is
shown in Figure 63. Individual Port architectures
are shown in
68., page
Figure 63. General I/O Port Architecture
General Port architecture
Port operating modes
Port Configuration Registers (PCR)
Port Data Registers
Individual Port functionality.
127. In general, once the purpose for a
ADDRESS
ALE
MACROCELL OUTPUTS
EXT CS
WR
ENABLE PRODUCT TERM ( .OE )
WR
WR
Figure 65., page 124
CONTROL REG.
CPLD- INPUT
DATA OUT
READ MUX
DIR REG.
G
D
D
D
D
REG.
P
D
B
Q
Q
Q
Q
DATA IN
uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
to
Figure
DATA OUT
ADDRESS
port pin has been defined, that pin is no longer
available for other purposes. Exceptions are not-
ed.
As shown in Figure 63, the ports contain an output
multiplexer whose select signals are driven by the
configuration bits in the Control Registers (Ports A
and B only) and PSDsoft Express Configuration.
Inputs to the multiplexer include the following:
–
–
–
–
The Port Data Buffer (PDB) is a tri-state buffer that
allows only one source at a time to be read. The
Port Data Buffer (PDB) is connected to the Internal
Data Bus for feedback and can be read by the
MCU. The Data Out and macrocell outputs, Direc-
tion and Control Registers, and port pin input are
all connected to the Port Data Buffer (PDB).
Output data from the Data Out register
Latched address outputs
CPLD macrocell output
External Chip Select (ECS1-ECS2) from the
CPLD.
OUTPUT
SELECT
OUTPUT
MUX
ENABLE OUT
MACROCELL
INPUT
PORT PIN
AI06604
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