UPSD3234AV-24U1T STMicroelectronics, UPSD3234AV-24U1T Datasheet - Page 81

• Manufacturer Part Number: UPSD3234AV-24U1T
• Description: Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM
• Manufacturer: STMicroelectronics

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DDC2B Protocol
DDC2B is constructed based on the Philips I
terface. However, in the level of DDC2B, PC host
is fixed as the master and the monitor is always re-
garded as the slave. Both master and slave can be
operated as a transmitter or receiver, but the mas-
ter device determines which mode is activated. In
this protocol, address pointer is also used.
According to DDC2B specification, A0 (for WRITE
Mode) and A1 (for READ Mode) are assigned as
the default address of monitors.
Figure 43. Conceptual Structure of the DDC Interface
DDC2B/DDC2AB
command received
DDC2B/DDC2AB
Utilities
SWENB = 1
Service Routines
I2C interface
(H/W)
uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
I2C
Check Mode flag in DDCCON
Mode = 1 Mode = 1 Mode = 0
2
C in-
DDC Interrupt
vector address
(
0023H
DDC2B
Utilities
The reception of the incoming data in WRITE
Mode or the updating of the outgoing data in
READ Mode should be finished within the speci-
fied time limit. If software in the slave’s side cannot
react to the master in time, based on I
SCL pin can be stretched low to inhibit the further
action from the master. The transaction can be
proceeded in either byte or burst format.
DDC2B
SWENB =1
)
DDC Transmitter
DDC1.
Utilities
(H/W)
D DC2B
SWENB =0
AI06645
2
C protocol,
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