UPSD3234AV-24U1T STMicroelectronics, UPSD3234AV-24U1T Datasheet - Page 77

• Manufacturer Part Number: UPSD3234AV-24U1T
• Description: Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM
• Manufacturer: STMicroelectronics

www.DataSheet4U.com
Table 61. Description of the DDCON Register Bits
Bit
7
6
5
4
3
2
1
0
DDC1_Int
DDC_AX
DDC1EN
SWHINT
Symbol
EX_DAT
SWENB
Mode
—
Reserved
0 = The SRAM has 128 bytes (Default)
1 = The SRAM has 256 bytes
Note: This bit is valid for DDC1 & DDC2b Modes
0 = Data is automatically read from SRAM at the current location of DDCADR and sent
out via current DDC protocol. (Default)
1 = MCU is interrupted during the current data byte transmission period to load the next
byte of data to send out.
Note: This bit is valid for DDC1 & DDC2b Modes
0 = Data is automatically read from SRAM at the current location of DDCADR and sent
out via current DDC protocol. (Default)
1 = MCU is interrupted during the current data byte transmission period to load the next
byte of data to send out.
This bit only affects DDC2b Mode Operation:
0 = DDC2b I2C Address is A0/A1 (default)
1 = DDC2b I2C Address is AX. Least 3 significant address bits are ignored.
For DDC1 Mode Operation Only:
0 = No DDC1 Interrupt
1 = DDC1 Interrupt request. Set by HW and should be cleared by SW interrupt service
routine.
Note1: This bit is set in the 9th V
0 = DDC1 Mode is disabled – V
The DDC unit will still respond to DDC2b requests. –provided I2C enabled.(Default)
1 = DDC1 Mode is enabled.
Set by hardware when the DDC unit switches from DDC1 to DDC2b Modes.
0 = No interrupt request.
1 = Switch to DDC2b Mode (Interrupt pending)
Set by HW and should be cleared by SW interrupt service routine.
Note1: This bit has no connection with SWENB.
Current Mode Indication Bit:
0 = Unit is in DDC1 Mode
1 = Unit is in DDC2b Mode
Note: When the DDC unit transitions to DDC2b Mode, the DDC unit will stay in DDC2b
Mode until the DDC unit is disabled, or the system is reset.
uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
SYNC
CLK
at DDC1 Enable Mode. (SWENB=1)
is ignored.
Function
77/170