UPSD3234AV-24U1T STMicroelectronics, UPSD3234AV-24U1T Datasheet - Page 72

• Manufacturer Part Number: UPSD3234AV-24U1T
• Description: Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM
• Manufacturer: STMicroelectronics

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uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
Table 51. Description of the SxCON Bits
Table 52. Selection of the Serial Clock Frequency SCL in Master Mode
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CR2
Bit
7
6
5
4
3
2
1
0
0
0
0
0
1
1
1
1
Symbol
ADDR
CR2
STO
CR1
CR0
CR1
ENII
STA
AA
0
0
1
1
0
0
1
1
This bit along with Bits CR1and CR0 determines the serial clock frequency when SIO is
in the Master Mode.
Enable IIC. When ENI1 = 0, the IIC is disabled. SDA and SCL outputs are in the high
impedance state.
START flag. When this bit is set, the SIO H/W checks the status of the I
generates a START condition if the bus free. If the bus is busy, the SIO will generate a
repeated START condition when this bit is set.
STOP flag. With this bit set while in Master Mode a STOP condition is generated.
When a STOP condition is detected on the I
flag.
Note: This bit have to be set before 1 cycle interrupt period of STOP. That is, if this bit is
set, STOP condition in Master Mode is generated after 1 cycle interrupt period.
This bit is set when address byte was received. Must be cleared by software.
Acknowledge enable signal. If this bit is set, an acknowledge (low level to SDA) is
returned during the acknowledge clock pulse on the SCL line when:
• Own slave address is received
• A data byte is received while the device is programmed to be a Master Receiver
• A data byte is received while the device is a selected Slave Receiver. When this bit is
reset, no acknowledge is returned.
SIO release SDA line as high during the acknowledge clock pulse.
These two bits along with the CR2 Bit determine the serial clock frequency when SIO is
in the Master Mode.
CR0
0
1
0
1
0
1
0
1
f
OSC
120
240
480
960
Divisor
16
24
30
60
12MHz
12.5
6.25
375
250
200
100
50
25
Function
2
C-bus, the I
Bit Rate (kHz) at f
24MHz
12.5
750
500
400
200
100
50
25
2
C hardware clears the STO
36MHz
18.75
37.5
750
600
300
150
75
X
OSC
2
C-bus and
40MHz
833
666
333
166
83
41
20
X