UPSD3234AV-24U1T STMicroelectronics, UPSD3234AV-24U1T Datasheet - Page 125

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UPSD3234AV-24U1T

Manufacturer Part Number
UPSD3234AV-24U1T
Description
Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM
Manufacturer
STMicroelectronics
Datasheet
www.DataSheet4U.com
Port C – Functionality and Structure
Port C can be configured to perform one or more
of the following functions (see Figure 66):
Figure 66. Port C Structure
Note: 1. ISP or battery back-up
MCU I/O Mode
CPLD Output – McellBC7-McellBC0 outputs
can be connected to Port B or Port C.
CPLD Input – via the Input Macrocells (IMC)
In-System Programming (ISP) – JTAG pins
(TMS, TCK, TDI, TDO) are dedicated pins for
device programming. (See
IN-CIRCUIT USING THE JTAG SERIAL
INTERFACE, page
on JTAG programming.)
MCELLBC [ 7:0 ]
ENABLE PRODUCT TERM ( .OE )
WR
WR
134, for more information
CPLD - INPUT
READ MUX
DATA OUT
DIR REG.
PROGRAMMING
D
D
REG.
P
D
B
Q
Q
uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
DATA IN
SPECIAL FUNCTION
DATA OUT
Port C does not support Address Out Mode, and
therefore no Control Register is required.
1
Open Drain – Port C pins can be configured in
Open Drain Mode
Battery Backup features – PC2 can be
configured for a battery input supply, Voltage
Stand-by (V
PC4 can be configured as a Battery-on
Indicator (V
less than V
SPECIAL FUNCTION
OUTPUT
OUTPUT
SELECT
MUX
ENABLE OUT
BAT
BATON
STBY
MACROCELL
.
1
INPUT
).
), indicating when V
CONFIGURATION
PORT C PIN
BIT
CC
125/170
AI06618
is

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