UPSD3234AV-24U1T STMicroelectronics, UPSD3234AV-24U1T Datasheet - Page 111

• Manufacturer Part Number: UPSD3234AV-24U1T
• Description: Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM
• Manufacturer: STMicroelectronics

www.DataSheet4U.com
Page Register
The 8-bit Page Register increases the addressing
capability of the MCU Core by a factor of up to 256.
The contents of the register can also be read by
the MCU. The outputs of the Page Register
(PGR0-PGR7) are inputs to the DPLD decoder
and can be included in the Sector Select (FS0-
FS7, CSBOOT0-CSBOOT3), and SRAM Select
(RS0) equations.
Figure 57. Page Register
RESET
D0 - D7
R / W
uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
D0
D1
D2
D3
D4
D5
D6
D7
REGISTER
PAGE
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
If memory paging is not needed, or if not all 8 page
register bits are needed for memory paging, then
these bits may be used in the CPLD for general
logic.
Figure
flops in the register are connected to the internal
data bus D0-D7. The MCU can write to or read
from the Page Register. The Page Register can be
accessed at address location CSIOP + E0h.
PGR0
PGR1
PGR2
PGR3
PGR4
PGR5
PGR6
PGR7
57
shows the Page Register. The eight flip-
DPLD
CPLD
AND
PLD
INTERNAL PSD MODULE
SELECTS
AND LOGIC
AI05799
111/170