UPSD3234AV-24U1T STMicroelectronics, UPSD3234AV-24U1T Datasheet - Page 41
UPSD3234AV-24U1T
Manufacturer Part Number
UPSD3234AV-24U1T
Description
Flash Programmable System Devices with 8032 Microcontroller Core and 64Kbit SRAM
Manufacturer
STMicroelectronics
Datasheet
1.UPSD3234AV-24U1T.pdf
(170 pages)
- Current page: 41 of 170
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Idle Mode
The instruction that sets PCON.0 is the last in-
struction executed in the normal operating mode
before Idle Mode is activated. Once in the Idle
Mode, the CPU status is preserved in its entirety:
Stack pointer, Program counter, Program status
word, Accumulator, RAM and All other registers
maintain their data during Idle Mode.
There are three ways to terminate the Idle Mode.
–
Activation of any enabled interrupt will cause
PCON.0 to be cleared by hardware
terminating Idle mode. The interrupt is
serviced, and following return from interrupt
instruction RETI, the next instruction to be
executed will be the one which follows the
instruction that wrote a logic '1' to PCON.0.
uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV
–
–
Power-Down Mode
The instruction that sets PCON.1 is the last exe-
cuted prior to going into the Power-down Mode.
Once in Power-down Mode, the oscillator is
stopped. The contents of the on-chip RAM and the
Special Function Register are preserved.
The Power-down Mode can be terminated by an
external RESET.
External hardware reset: the hardware reset is
required to be active for two machine cycle to
complete the RESET operation.
Internal reset: the microcontroller restarts after
3 machine cycles in all cases.
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