SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 123

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

SPC8106
13. A control bit in Auxiliary Register 1 allows selecting the power save mode state of the LCD interface signals.
14. The output pin IREFEN# should be used to control the current reference source for the external RAMDAC.
15. When the MEMEN pin is selected as the refresh clock source, this input will not be masked during Power
16. If AUX[0B] bit 2 = 1, then reads to the I/O addresses 3C6h, 3C8h, and 3C9h will be decoded as external
17. In active mode if the CRT is enabled, the logic value on the D477 pin is determined by AUX[0B] bit 4.
18. In order to properly make use of SLEEP mode of the RAMDAC, software is required to program the sleep bit
19. In Power Save Modes 3 and 4 you cannot access the LUT/RAMDAC. However, if the LUT/RAMDAC is writ-
20. If AUX[06] bit 4=1, RS2 remains active and D447 remains L in LCD only mode or in any Power Save modes.
21. In Software Power Save Modes 3 and 4, software may set AUX[03] bit 3 to force DACRD# and DACWR#
411-1.0
nals are returned to their active driving states. This sequencing of the LCDPWR# and interface signals is
done to protect the panel from being damaged from DC signals applied to the interface while the Sequencer
is stopped and all chip output signals are inactive.
In power save modes, the LCD interface signals can all be driven low, or can be put into a high-impedance
state, as selected by this option.
When IREFEN# is high, the current reference should be shut off - this will ensure that the DAC analog cir-
cuitry is not active. When IREFEN# is low, the current reference should be enabled. If a voltage reference is
used for the RAMDAC, then IREFEN# is not required and may be left unconnected.
Save Mode 4 or Suspend mode.
RAMDAC reads. If AUX[0B] bit 2 = 0, then reads to these I/O addresses will access the internal LUT regis-
ters. For CRT modes, this bit should be set to 1. If CRT mode is enabled, and the chip is in active mode,
Power Save Mode 1 or Power Save Mode 2, then writes to these I/O addresses and 3C7h will result in data
being written to both the internal LUT registers and the external RAMDAC registers. Reads from 3C7h will al-
ways return the internal RAMDAC/Lookup Table Status Register.
in the external RAMDAC control register on system initialization. When the SPC8106 forces the D477 pin
high in power save modes, the RAMDAC will enter sleep mode if this bit has been programmed correctly.
ten to in this mode, the last I/O write will actually get written.
high. This can be used to further reduce system power consumption.
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
X12-SP-001-07
Hardware Functional Specification
SP1-81