SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 59

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

SPC8106
Pin Name
MEMW#
IOEN#
READY
RESET
IRQ
MEMCS16# O
IOCS16#
BHE#
Pin Name
MA[0:9]
MD[0:15]
411-1.0
Type Pin #
I
I
O
I
O
O
I
Type
O
I/O
*
*
*
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
*
98
93
142
141
103
99
100
101
Pin #
57, 55,
53, 51,
48, 52,
54, 56,
58, 20
81, 79,
77, 75,
70, 68,
66, 64,
63, 65,
67, 69,
74, 76,
78, 80
Drv
TS2
(* C)
TTL/
TS2U2
Table 0-1 CPU Interface Pins (Continued)
Drv
TTLS
TTLS
TS3
(* C)
TTLS
TS3
TS4
(* C)
TS4
(* C)
TTL
Table 0-2 Video Memory Interface Pins
Description
Multiplexed row/column address bits for video display memory.
Data bits for video display memory. The output drivers of these pins are
placed into a high-impedance state when RESET is high, or when the
Sequencer is in a reset state. On the falling edge of RESET, the values
on MD[3:0] and MD[12:9] are latched into a read-only Auxiliary Register
and are available to be read as configuration inputs. Also, the value on
MD[8:4] and MD[15:13] are used to configure various hardware options.
See “Power On / Reset Options” on page 22 for details.
Description
ISA Bus System Memory Write Strobe. In Suspend Mode the
MEMW# input is disabled.
ISA Bus I/O Enable. This input should be connected to the ISA bus
AEN signal. When this signal is high, I/O address decoding is
disabled. In Suspend Mode, the IOEN# input is disabled.
ISA Bus READY signal. This output is driven low to force the CPU to
insert wait states during memory cycles. READY is released to high-
Z after a transfer is complete.
The active high Reset signal from the CPU clears all internal
registers and forces all signals to their inactive state.
ISA Bus Vertical Interrupt. When enabled, a Vertical Retrace
Interrupt will cause this signal to be driven from a logic 0 state to a
logic 1 (rising-edge triggered interrupt). Once set, this interrupt must
be cleared by a bit in the CRTC registers. A control bit in the Auxiliary
Registers allows this output to be optionally disabled (tri-stated). This
pin also is used for the output of the NAND tree in pin test mode.
ISA Bus Memory Chip Select 16. Address inputs LA[23:17] are
decoded to drive this output low when a valid memory address
(AXXXXh, BXXXXh) appears on the bus.
ISA Bus I/O Chip Select 16. Address inputs A[15:0] and IOEN# are
decoded to drive this output low when a valid SPC8106 I/O register
address appears on the bus,. Note that I/O addresses 3C6h-3C9h do
not result in IOCS16# being driven low (i.e. RAMDAC and internal
LUT register reads and writes are 8 bit cycles).
ISA Bus Byte High Enable. In Suspend Mode the BHE# input is
disabled.
X12-SP-001-07
Hardware Functional Specification
SP1-17