SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 89

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

Tv
Ty
Tx
SPC8106
Symbol
t3a
t3b
411-1.0
t1
t2
t4
t5
t6
t7
t8
t9
= internal vertical retrace period
= 393,216Ts if CLKI or self-refresh mode is selected
(approximately 13.9 ms for 28.322 MHz, 15.7 ms for 25.175 MHz)
= 1024 Tm if MEMEN Refresh clock source is selected
= 1024 Tp if 64 kHz PDCLK Refresh clock source is selected
= 512 Tp if 32 kHz PDCLK Refresh clock source is selected
= HSYNC# period (typically 31.8 s)
= VSYNC# periods (typically 14.3 ms or 16.7 ms, depending on video mode
SUSPEND# asserted to IREFEN#, D477 driven high, and
RS2, OL0, OL1, OL23, BLANK#, HSYNC#, VSYNC#
driven low.
SUSPEND# asserted to PCLK, DACRD#, DACWR# high-
impedance
SUSPEND# negated to IREFEN#, D477 driven low, and
RS2, OL0, OL1, OL23, BLANK#, HSYNC#, VSYNC#
active.
(CLKI selected as refresh clock source)
SUSPEND# negated to IREFEN#, D477 driven low, and
RS2, OL0, OL1, OL23, BLANK#, HSYNC#, VSYNC#
active.
(self-refresh, MEMEN or PDCLK selected as refresh clock
source)
SUSPEND# negated to DACRD#, DACWR# driven high,
PCLK driven (halted)
IREFEN# negated to PD[7:0] inactive
IREFEN# asserted to PD[7:0], PCLK active
IREFEN# negated to LCAS#, UCAS# asserted (to initialize
DRAM self-refresh mode)
IREFEN# asserted to RAS#, LCAS#, UCAS# negated
(terminate DRAM self-refresh mode)
IREFEN# asserted to PCLK active
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
Table 0-34 Suspend Mode CRT Signal Timing
Parameter
X12-SP-001-07
Tv+3Ts
Min
2Ty
Ts
Hardware Functional Specification
Typ
3Ty+4Ts
2Tv+4Ts
Max
20Ts
80Tx
10Ts
20Ts
4Ts
20
20
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
SP1-47