SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 138

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

bit 3
bit 2
bit 1
bit 0
bit 7
bit 6
Hardware Functional Specification
07 Extended Function Register 2 RW
Mode 13h 32/
64 Gray
Select
SP1-96
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Dithering
Control
Page Select Register Port Enable
Setting this bit to 1 enables access to the Page Select Register at port 3CDh. Setting this bit to 0
disables access to this register.
Horizontal Non-display Period Width
Setting this bit to 1 forces the Horizontal Non-display Period to 20 fast/10 slow character clocks.
Setting this bit to 0 forces the Horizontal Non-display Period to 14 fast/7 slow character clocks. This
bit has an effect only when AUX[0B] bit 1 (CRT Enable) is set to 0.
Sequencer CPU Cycles Disable
Setting this bit to 1 prevents the Sequencer from generating DRAM cycles from a CPU R/W
request. Any subsequent memory read cycles will read the contents of the 32-bit display latch. A
memory write with this bit set is an invalid cycle and will have no effect.
LCD Power Disable
Setting this bit to 1 forces the LCDPWR# output pin high so that panel power can be turned off.
Mode 13h 32/64 Gray Select
This bit allows the selection of 32 or 64 gray shades on a monochrome LCD panel when in mode
13h (256 Color Mode, Graphics Controller Mode Register index [05], bit 6 Mode13h Select = 1).
When this bit = 0, 64 gray shades are displayed in mode 13h (16 gray levels by FRM + dithering).
When this bit = 1, then 32 gray shades are displayed in mode 13h (16 gray levels by FRM + dither-
ing). This bit has no effect on an image displayed on a CRT display.
Dithering Control
This bit is used to control the dithering logic for the monochrome LCD display. When this bit = 0,
dithering is enabled for mode 13h (Graphics Controller register [05] bit 6 = 1) and disabled for other
modes - this is the normal setting to provide 64 gray shades in mode 13h. When this bit = 1, then
dithering is disabled for mode 13h. This bit has no effect on an image displayed on a CRT display.
Dithering is also disabled in Power Save Mode 5.
Dual/Single
Table 0-53 Horizontal Non-Display Period Width
(1/0)
Auto Disable
Line/Pixel
Doubling
0
0
1
1
Slow/Fast
(1/0)
Reserved
Test Bit
0
1
0
1
X12-SP-001-07
One Character Clock
Reserved
Test Bit
16Ts
16Ts
32Ts
8 Ts
Reserved
Test Bit
Graphics
VExpand
Enable
Text
VExpand
Enable
411-1.0
SPC8106