SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 77

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

7.5
This table refers to CPU bus timing when configuration input MD[5] = 1 on the falling edge of
RESET. In this case, processor address lines PA[23:2] may be connected to address inputs
LA[23:17] and A[16:2]. These inputs will be latched by the SPC8106 on the rising edge of the ALE
input pin. Note that the ALE pin should be driven by the ADS# signal from the CPU. Address
inputs A[1:0] should be connected to the ISA bus address outputs A[1:0].
SPC8106
Symbol
Figure 8 : CPU Bus Cycle Timing - 16-bit I/O - Modified Address
411-1.0
t1
t2
t3
t4
t5
t6
CPU Bus Cycle Timing - 16-bit I/O (Modified Address Timing)
ADS# pulse width
IOEN# active setup IOR#, IOW# asserted
A[15:2] valid setup to ADS# asserted
A[15:2] valid hold from ADS# negated
A[15:2] valid setup to IOR#, IOW# asserted
A[1:0], BHE# valid setup to IOR#, IOW# asserted
ISA bus outputs, using PA[23:2] connected to LA[23:17], A[16:2]
ADS# connected to ALE pin (MD[5] = 1 @ RESET)
ALE
(driven
by ADS#)
IOEN#
A[15:2]
A[1:0]
BHE#
IOR#
IOW#
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
Table 0-24 CPU Bus Cycle Timing - 16-bit I/O - Modified Address Timing
Parameter
t3
t2
valid
t5
t1
t6
X12-SP-001-07
valid
t4
Timingsource: 8106_cpu_bus16_ioma_01.can
Min
30
50
10
10
10
0
Hardware Functional Specification
Typ
Max
Units
ns
ns
ns
ns
ns
ns
SP1-35