SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 23

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

Power Save Mode Control
Power Supply
SPC8106
Pin Name
SUSPEND# I
PDCLK
Pin Name
COREVDD
IOVDD
VSS
IOVSS
411-1.0
Type
I
Type Pin #
P
P
P
P
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
14, 37,
85, 92,
109
1, 50, 73,
124
11, 36,
88, 89,
108
49, 72,
123, 144
Pin #
84
143
Description
V DD supply for core logic.
V DD supply for interface pins.
V SS supply for core logic.
V SS supply for interface pins.
Description
A low level on this pin puts the chip into a hardware power down mode. The
SUSPEND# signal overrides any software initiated power down modes, and
disables the ISA-Bus interface inputs except RESET. Address and Data inputs are
also masked when this signal is low. When in Suspend Mode the UD(3:0), LD(3:0),
XSCL, XSCL2, LP, YD and WF signals are driven into a high impedance or low
state (configurable) and the LCDPWR# signal is driven high.
Power Down Clock. This input may be used to provide a low frequency clock for
generating refresh in Power Save Modes 4 and Suspend, as an optional
alternative to using the pixel clock or MEMEN input as the refresh clock source.
This clock input should be driven by either by a 32 kHz 50% duty cycle clock
source, or a 64 kHz clock source with a high period as short as possible (but >
minimum RAS low pulse width) to minimize DRAM current consumption during
refresh. The PDCLK input is used to directly generate the RAS and CAS pulses
during Power Save Mode 4 and Suspend.
Data Sheet
DS-17