SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 280

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

Each VGA memory address spans four planes of data (to give 32 bits). Sprite images consist of
only two bits per pixel. Each VGA memory address therefore contains sixteen pixels of sprite
image. One complete row of a sprite image (64 pels) is held in four sequential VGA memory
addresses. 256 addresses (x 4 planes = 1KB) are required to hold a complete sprite image.
For cursor images (typically 32 x 32 pels) only 1/4 of the entire sprite area is required. In this situ-
ation the remaining 3/4 of the sprite should be set to transparent (AND pels = 1 and XOR pels =
0). When less than entire 64 rows are required as in the case of a 32x32 cursor, it is more CPU
efficient to place the image in the lower portion of the sprite memory, because CPU fetches to
video memory are reduced. The recommended location for a 32x32 cursor data is starting at the
256th byte when using Sprite Write Mode. The Y Start Row Register CRTC [35h] should then be
set to clip the upper portion of the cursor data (i.e., the undisplayed portion). Unfortunately, for
each row or partial row displayed, the full width of the row (all 64 pels) is read into an internal
buffer for display, and CPU efficiency cannot be improved.
The following example demonstrates how to load a sprite image (64 x 64) into slot 256 (offset 0 in
the upper 256K).
Programming Notes and Examples
SP3-54
/* Defines */
/*---------*/
#define AUX 0x3DE
#define CRTC 0x3D4
char far* pDisplayMem, pImgData;
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
Even (XOR) Mask
Bytes 0~3 (Pels 0~31)
E0
E1
E2
E3
E0
B0
E2
B1
O0
B0
O2
B2
E1
B1
B3
E3
O1
B2
O3
B3
X12-AN-003-02
Resulting Display of Bytes 0~3
(Pixels 0~31 Within the Sprite)
Odd (AND) Mask
Bytes 0~3 (Pels 0~31)
O0
O1
O2
O3
411-1.0
SPC8106