SPC8106 S-MOS Systems, SPC8106 Datasheet - Page 159

• Manufacturer Part Number: SPC8106
• Description: LCD/CRT VGA CONTROLLER
• Manufacturer: S-MOS Systems

The internal LUT Register I/O address space is also used to address the 4 sprite palette loca-
tions. This internal sprite palette operates similarly to the external palette supported in the 477-
type RAMDAC and may be accessed via the internal LUT address space when the External DAC
RS2 Bit (AUX[0B] bit 3) is set to 1.
The internal LUT registers can be configured as either a 256x6 gray scale lookup table for mono-
chrome LCD displays, or as a 256x12 color lookup table for color LCD displays (4 bits each of R,
G, B). The lookup table configuration is selected by the value in AUX[02] bit 6. Similarly, this set-
ting determines whether the internal sprite palette registers are configured as a 4x6 bit gray scale
palette or a 4x12 bit color palette (4 bits each of R, G, B).
bits 7-0
bits 1-0
bits 7-0
SPC8106
Dummy LCD Lookup Table Pixel Mask Register
3C6h RW
Dummy
LUT Pixel
Mask Bit 7
RAMDAC/Lookup Table Status Register
3C7h RO
n/a
LCD Lookup Table Read Address Register
3C7h WO
Lookup
Table Read
Addr Bit 7
411-1.0
Dummy
LUT Pixel
Mask Bit 6
n/a
Lookup
Table Read
Addr Bit 6
S-MOS Systems, Inc. • Tel: [phone] • Fax: [phone] • http://www.smos.com
Dummy LCD Lookup Table Pixel Mask Bits [7:0]
This register contains 8 read/write bits that have no effect in hardware. These bits are provided for
compatibility with some software that expects to use the value stored in this register while in LCD
mode.
RAMDAC/Lookup Table Status Bits [1:0]
Directly after a write to I/O address 3C7h (Lookup Table or RAMDAC Read Address Register), the
Read/Write Mode Status bits 1-0 are both set to 1. Directly after a write to I/O address 3C8h
(Lookup Table or RAMDAC Write Address Register), both these bits are set to 0.
LCD Lookup Table Read Address Bits [7:0]
These 8 bits are used to select 1 of 256 gray scale/color lookup table registers to be read, when
AUX[0B] bit 3 = 0.
When AUX[0B] bit 3 = 1, then this read address is used to select 1 of 4 internal sprite palette regis-
ters. In this case, only read addresses 0Ch - 0Fh select a valid sprite palette location. (In the cur-
rent implementation, only the low 2 bits of the read address are actually decoded to select 1 of 4
internal sprite palette registers. However, the specific addresses 0Ch-0Fh should be used to main-
tain compatibility with the overlay registers used in the external RAMDAC.)
Dummy
LUT Pixel
Mask Bit 5
n/a
Lookup
Table Read
Addr Bit 5
Dummy
LUT Pixel
Mask Bit 4
n/a
Lookup
Table Read
Addr Bit 4
X12-SP-001-07
Dummy
LUT Pixel
Mask Bit 3
n/a
Lookup
Table Read
Addr Bit 3
Dummy
LUT Pixel
Mask Bit 2
n/a
Lookup
Table Read
Addr Bit 2
Hardware Functional Specification
Dummy
LUT Pixel
Mask Bit 1
Read Write
Mode
Status Bit 1
Lookup
Table Read
Addr Bit 1
Dummy
LUT Pixel
Mask Bit 0
Read Write
Mode
Status Bit 0
Lookup
Table Read
Addr Bit 0
SP1-117